And - Motorola DSP56800 Manual

AND

Operation:
S • D → D
S • D[31:16] → D[31:16]
where • denotes the logical AND operator
Description: Logically AND the source operand (S) with the destination operand (D) and store the result in the des-
tination. This instruction is a 16-bit operation. If the destination is a 36-bit accumulator, the source is
ANDed with bits 31–16 of the accumulator. The remaining bits of the destination accumulator are not
affected.
Usage: This instruction is used for the logical AND of two registers; the ANDC instruction is appropriate to
AND a 16-bit immediate value with a register or memory location.
Example:
AND
Before Execution
6 1234
A2 A1
X0
7F00
Explanation of Example:
Prior to execution, the 16-bit X0 register contains the value $7F00, and the 36-bit A accumulator con-
tains the value $6:1234:5678. The AND X0,A instruction logically ANDs the 16-bit value in the X0
register with bits 31–16 of the A accumulator (A1) and stores the 36-bit result in the A accumulator.
Bits 35–32 in the A2 register and bits 15–0 in the A0 register are not affected by this instruction.
Condition Codes Affected:
15 14
LF *
See Section 3.6.5, "16-Bit Destinations," on page 3-35 for cases with X0, Y0, or Y1 as D.
See Section 3.6.2, "36-Bit Destinations—CC Bit Set," on page 3-34 and Section 3.6.4, "20-Bit Desti-
nations—CC Bit Set," on page 3-34 for the case when the CC bit is set.
Instruction Fields:
Operation
AND
Timing:
2 oscillator clock cycles
Memory: 1 program word
Logical AND
(no parallel move)
(no parallel move)
X0,A
5678
A0
MR
13 12 11 10 9
* * * * I1
N — Set if bit 31 of A or B result is set
Z — Set if bits 31–16 of A or B result are zero
V — Always cleared
Operands C
DD,FDD 2
F1,DD
Instruction Set Details
Assembler Syntax:
AND S,D
AND S,D
; AND X0 with A1
After Execution
6 1200
A2 A1
X0
7F00
CCR
8 7 6 5 4
I0 SZ L E U
W
1 16-bit logical AND
AND
(no parallel move)
(no parallel move)
5678
A0
3 2 1 0
N Z V
C
Comments
A-35