Table A-2 Address Generation Unit (Agu) Registers; Table A-3 Data Alu Registers - Motorola DSP56800 Manual

Table A-2 shows the register set available for use as pointers in address-register-indirect addressing
modes. The most common fields used in this table are Rn and Rj. This table also shows the notation used
for AGU registers in AGU arithmetic operations.
Register Field Registers in This Field
Rn
Rj R0, R1, R2, R3
N
M01
Table A-3 shows the register set available for use in data ALU arithmetic operations. The most common
field used in this table is FDD.
Register Field Registers in This Field
FDD
F1DD
DD
F
F1
Address operands used in the instruction field sections of the instruction descriptions are given in
Table A-4. Addressing mode operators that are accepted by the assembler for specifying a specific
addressing mode are shown in Table A-5.
A-2
Table A-2. Address Generation Unit (AGU) Registers
R0-R3 Five AGU registers available as pointers for addressing and as
SP sources and destinations for move instructions
Four pointer registers available as pointers for addressing
N One index register available only for indexed addressing modes
M01 One modifier register
Table A-3. Data ALU Registers
A, B Five data ALU registers—two 36-bit accumulators and three 16-bit
X0, Y0, Y1 data registers accessible during data ALU operations
Contains the contents of the F and DD register fields
A1, B1 Five data ALU registers—two 16-bit MSP portions of the
X0, Y0, Y1 accumulators and three 16-bit data registers accessible during data
ALU operations
X0, Y0, Y1 Three 16-bit data registers
A, B Two 36-bit accumulators accessible during parallel move instruc-
tions and some data ALU operations
A1, B1 The 16-bit MSP portion of two accumulators accessible as source
operands in parallel move instructions
DSP56800 Family Manual
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