Data Arithmetic Logic Unit
$AAAA
16
Multi-Bit
Shifting Unit
EXT
MSP
A
F
F
A
A
35 32 31
Example: Right Shifting (ASRR)
Figure 3-3. Right and Left Shifts Through the Multi-Bit Shifting Unit
After shifting, the extension register is always loaded with zero extension for logical shifts or sign
extension for arithmetic shifts. For right shifts, the LSP is set to zero except for the ASRAC and LSRAC
instructions, where the lower bits are shifted into the LSP. For left shifts, the upper bits are not shifted into
the extension register, and the LSP is always set to zero.
3.1.5
Accumulator Shifter
The accumulator shifter is an asynchronous parallel shifter with a 36-bit input and a 36-bit output. The
operations performed by this unit are as follows:
•
No shift performed—ADD, SUB, MAC, and so on
•
1-bit left shift—ASL, LSL, ROL
•
1-bit right shift—ASR, LSR, ROR
•
Force to zero—MPY, IMPY(16)
The output of the shifter goes directly to the MAC unit as an input.
3.1.6
Data Limiter and MAC Output Limiter
The data ALU contains two units that implement optional saturation of mathematical results, the Data
Limiter and the MAC Output Limiter. The Data Limiter saturates values when data is moved out of an
accumulator with a move instruction or parallel move. The MAC Output Limiter saturates the output of the
data ALU's MAC unit.
Section 3.4, "Saturation and Data Limiting," provides an in-depth discussion of saturation and limiting, as
well as a description of the operation of the two limiter units.
3-6
$4
4
LSP
A
0
0
0
0
16 15
0
DSP56800 Family Manual
$AAAA
$4
16
Multi-Bit
Shifting Unit
EXT
MSP
A
F
A
A
A
0
35 32 31
16 15
Example: Left Shifting (ASLL)
4
LSP
0
0
0
0
0
AA0039