Motorola DSP56800 Manual page 440

CLR A-64
CMP A-66
Compare CMP A-66
comparing 3-18
condition code (CC) bit 3-33
condition code computation A-7
condition code generation 3-33
Condition Code Register (CCR) 5-6
Condition Codes
carry (C) condition 5-7
effect of CC bit A-11
effect of SA bit A-11
extension in use (E) condition 5-8
limit (L) condition 5-8
negative (N) condition 5-7
overflow (V) condition 5-7
size (SZ) condition 5-8
unnormalized (U) condition 5-8
zero (Z) condition 5-7
convergent rounding 3-30
core global data bus (CGDB) 2-5
D
data ALU input registers (X0, Y1, and Y0) 3-4
Data ALU, see Data Arithmetic Logic Unit (ALU)
Data Arithmetic Logic Unit (ALU) 2-3
accumulator registers (A and B) 3-4
accumulator shifter 3-6
barrel shifter 3-5
,
Data Limiter 3-6 3-26
input registers (X0, Y1, and Y0) 3-4
logic unit 3-5
MAC Output Limiter 3-6
multiply-accumulator (MAC) 3-5
, ,
Data Limiter 3-2 3-6 3-26
DEBUG A-68
debug processing state 7-1
DEC(W) A-69
Decrement Word DEC(W) A-69
digital signal processing 1-6
digital-to-analog 1-6
DIV A-71
Divide Iteration DIV A-71
,
division 3-21 8-13
,
fractional 3-21 8-13
,
integer 3-21 8-13
DO A-73
DO looping 5-15
DO loops 8-20
DSP56800 1-1
DSP56800 core 1-2
Index-ii
, , , ,
3-34 3-35 3-36 5-12
,
A-10
,
A-8
,
A-8
,
A-9
,
A-10
,
A-7
,
A-9
,
A-10
,
3-1
,
3-28
,
7-22
DSP56800 Family Manual
E
,
E condition bit 5-8 A-8
End Current DO Loop ENDDO A-77
ENDDO A-77
Enter Debug Mode DEBUG A-68
EOR A-79
EORC A-81
EX, see external X memory (EX)
exception processing state 7-1
extension register (A2 or B2) 3-4
external data memory 2-7
external X memory (EX) 5-11
F
fractional arithmetic 3-14
,
fractional division 3-21 8-13
fractional multiplication 3-19
H
hardware interrupt sources 7-10
Hardware Stack (HWS) 5-6
I
I1 and I0 interrupt mask bits 5-8
ILLEGAL A-83
Illegal Instruction Interrupt ILLEGAL A-83
IMPY(16) A-84
INC(W) A-86
Increment Word INC(W) A-86
incrementer/decrementer unit 4-5
indexes 8-26
instruction decoder 5-3
instruction execution pipelining 6-30
instruction formats 6-3
instruction groups 6-6
instruction latch 5-3
Instruction Processing 6-30
instruction set restrictions A-26
instruction set summary 6-17
instruction timing A-16
,
integer arithmetic 3-14 3-20
,
integer division 3-21 8-13
integer multiplication 3-20
Integer Multiply IMPY(16) A-84
interrupt arbitration 7-12
interrupt control unit 5-3
interrupt latency 7-16
interrupt mask (I1 and I0) 5-8
interrupt pipeline 7-14
interrupt priority level (IPL) 5-3
Interrupt Priority Register (IPR) 7-9
interrupt priority structure 7-8
interrupt sources 7-9
,
7-5