Figure 9-1 Jtag/Once Interface Block Diagram; Jtag Port - Motorola DSP56800 Manual

JTAG and On-Chip Emulation (OnCE™)
External
Interface
As already noted, the JTAG module is the master. It enables interaction with the debug services provided
by the OnCE, and its external serial interface is used by the OnCE port for sending and receiving
debugging commands and data.
9.2

JTAG Port

Problems associated with testing high-density circuit boards have led to the development of a proposed
standard under the sponsorship of the Test Technology Committee of IEEE and the Joint Test Action
Group (JTAG). The resulting standard, called the IEEE Standard Test Access Port and Boundary-Scan
Architecture, specifies industry-standard, in-circuit device testing and diagnosis. The DSP56800 family
provides a dedicated test access port (TAP) that is fully compatible with this standard, commonly referred
to as the "JTAG port."
This section provides an overview of the capabilities of the JTAG port as implemented on the DSP56800.
Information provided here is intended to supplement the supporting IEEE 1149.1a-1993 document, which
outlines the internal details, applications, and overall methodology of the standard. Specific details on the
implementation of the JTAG port for a given DSP56800-based device are provided in that device's user's
manual.
9-2
JTAG
Test
Access
Port
Controller
Figure 9-1. JTAG/OnCE Interface Block Diagram
DSP56800 Family Manual
OnCE
OnCE Command,
Status & Control
Breakpoint Logic
Trace Logic
Event Counter
Pipeline
Registers
FIFO
History
Buffer
XAB1
PAB
PDB
PGDB
PAB
AA0093