Figure 7-5 Interrupt Service Routine - Motorola DSP56800 Manual

Interrupt
Synchronized
and
Recognized
as Pending
Interrupt Control Cycle 1
Interrupt Control Cycle 2
Fetch
Decode
Execute
Instruction Cycle Count
i = Interrupt
ii = Interrupt Instruction Word
n = Normal Instruction Word
Figure 7-5 demonstrates the interrupt pipeline. The point at which interrupts are re-enabled and subsequent
interrupts are allowed is shown to illustrate the non-interruptible nature of the early instructions in the long
interrupt service routine.
Reset is a special exception, which will normally contain only a JMP instruction at the exception start
address.
There is only one case in which the stacked address will not point to the illegal instruction. If the illegal
instruction follows an REP instruction (see Figure 7-6), the processor will effectively execute the illegal
instruction as a repeated NOP, and the interrupt vector will then be inserted in the pipeline. The next
instruction will be fetched, decoded, and executed normally.
Vector Table
Main
Program
Jump Address
n1
n2
Explicit
Return From
Interrupt
(Should Be RTI)
(a) Instruction Fetches from Memory
Interrupt Synchronized and
Recognized as Pending
i
i
n1 n2 — Adr — ii2
n1 JSR JSR JSR JSR
n1 JSR JSR JSR JSR
1 2 3 4 5 6
(b) Program Controller Pipeline
Figure 7-5. Interrupt Service Routine
Interrupts and the Processing States
Interrupt
Subroutine
JSR
Interrupts Re-enabled
ii3 ii4 ii5 iin RTI
ii2 ii3 ii4 ii5 iin
ii2 ii3 ii4 ii5
7 8 9 10 11
Exception Processing State
Interrupt
PC Resumes
ii2
Operation
ii3
Interrupts
ii4
Re-enabled
Interrupt
Routine
iin
RTI
— — — — n2 —
RTI RTI RTI RTI RTI n2
iin RTI RTI RTI RTI RTI n2
12 13 14 15 16 17
AA0069
—
—
18
7-15