Bcc - Motorola DSP56800 Manual

Bcc

Operation:
If cc, then PC + label
else PC + 1
Description: If the specified condition is true, program execution continues at location PC + displacement. The PC
contains the address of the next instruction. If the specified condition is false, the PC is incremented,
and program execution continues sequentially. The offset is a 7-bit-sized value that is sign extended to
16 bits. This instruction is more compact than the Jcc instruction, but can only be used to branch within
a small address range
The term "cc" specifies the following:
CC (HS*)— carry clear (higher or same)
CS (LO*)— carry set (lower)
EQ — equal
GE — greater than or equal
GT — greater than
HI* — higher
LE — less than or equal
LS* — lower or same
LT — less than
NE — not equal
NN — not normalized
NR — normalized
* Only available when CC bit set in the OMR
X
+
•
⊕
Example:
LABEL
Explanation of Example:
In this example, if the Z bit is zero when executing the BNE instruction, program execution skips the
two INCW instructions and continues with the ADD instruction. If the specified condition is not true,
no branch is taken, the program counter is incremented by one, and program execution continues with
the first INCW instruction. The Bcc instruction uses a PC-relative offset of two for this example.
Restrictions:
A Bcc instruction used within a DO loop cannot begin at the LA or LA-1 within that DO loop.
A Bcc instruction cannot be repeated using the REP instruction.
A-48
Branch Conditionally
→ PC
→ PC
"cc" Mnemonic
denotes the logical complement of X
denotes the logical OR operator
denotes the logical AND operator
denotes the logical exclusive OR operator
BNE LABEL ; branch to label if Z condition clear
INCW A
INCW A
ADD B,A
DSP56800 Family Manual
Assembler Syntax:
Bcc <OFFSET7>
Condition
C=0
C=1
Z=1
N ⊕ V=0
Z+(N ⊕ V)=0
C • Z=1
Z+(N ⊕ V)=1
C+Z=1
N ⊕ V=1
Z=0
•
Z+(U E)=0
•
Z+(U E)=1
Bcc