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LSR
Condition Codes Affected:
15
14
LF
*
Instruction Fields:
Operation
LSR
Timing:
2 oscillator clock cycles
Memory:
1 program word
A-98
Logical Shift Right
MR
13
12
11
10
9
*
*
*
*
I1
L
— Set if data limiting has occurred during parallel move
N
— Always cleared
Z
— Set if A1 or B1 result equals zero
V
— Always cleared
C
— Set if bit 16 of A or B was set prior to the execution of the instruction
Operands
C
FDD
2
DSP56800 Family Manual
CCR
8
7
6
5
4
3
L
N
I0
SZ
E
U
W
1
1-bit logical shift right of word
LSR
2
1
0
Z
V
C
Comments
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