Motorola DSP56800 Manual page 370

NOTC
Operation:
X:<ea> → X:(ea)
D → D
Implementation Note:
This instruction is an alias to the BFCHG instruction, and assembles as BFCHG with the 16-bit imme-
diate mask set to $FFFF. This instruction will disassemble as a BFCHG instruction.
Description: Take the one's complement of the destination operand (D), and store the result in the destination. This
instruction is a 16-bit operation. If the destination is a 36-bit accumulator, the one's-complement is
performed on bits 31–16 of the accumulator. The remaining bits of the destination accumulator are not
affected. C is also modified as described in following discussion.
Example:
NOTC
Before Execution
R2
SR
Explanation of Example:
Prior to execution, the R2 register contains the value $CAA3. Execution of the instruction comple-
ments the value in R2. C is modified as described in following discussion.
Condition Codes Affected:
15 14
LF *
For destination operand SR:
For other destination operands:
A-140
Logical Complement with Carry
R2
CAA3
3456
MR
13 12 11 10 9
* * * * I1
? — Changed if specified in the field
C — Set if the value equals $FFFF before the complement
DSP56800 Family Manual
Assembler Syntax:
NOTC X:<ea>
NOTC D
After Execution
R2
SR
CCR
8 7 6 5 4
I0 SZ L E U
NOTC
355C
3456
3 2 1 0
N Z V C