Figure 3-8 Bit Weightings And Operand Alignments - Motorola DSP56800 Manual

16-Bit Word Operand
X0,Y0,Y1,A1,B1,
16-Bit Memory
32-Bit Long Word Operand
Y = Y1:Y0
36-Bit Accumulator
A,B
16-Bit Word Operand
X0,Y0,Y1,A1,B1,
16-Bit Memory
32-Bit Long Word Operand
in A1,B1
36-Bit Accumulator
A,B
The representation of numbers allowed on the DSP56800 architecture are as follows:
• Two's-complement values
• Fractional or integer values
• Signed or unsigned values
• Word (16-bit), long word (32-bit), or accumulator (36-bit)
The different representations not only affect the arithmetic operations, but also the condition code
generation. These numbers can be represented as decimal, hexadecimal, or binary numbers.
To maintain alignments of the binary point when a word operand is written to an accumulator A or B, the
operand is written to the most significant accumulator register (A1 and B1) and its most significant bit is
automatically sign extended through the accumulator extension register. The least significant accumulator
register is automatically cleared.
Some of the advantages of fractional data representation are as follows:
• The MSP (left half) has the same format as the input data.
• The LSP (right half) can be rounded into the MSP without shifting or updating the exponent.
0
-2
0
-2
4 0
-2 2
Fractional Two's-Complement Representations
31
-2
35 31
-2 2
Integer Two's-Complement Representations
Figure 3-8. Bit Weightings and Operand Alignments
Data Arithmetic Logic Unit
Fractional and Integer Data ALU Arithmetic
-15
2
-15 -16
2 2
-15 -16
2 2
15 14
-2 2
16 15
2 2
16 15
2 2
-31
2
-31
2
0
2
0
2
0
2
.
AA0041
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