Table 6-21 Conditional Register Transfer Instructions; Table 6-22 Data Alu Multiply Instructions - Motorola DSP56800 Manual

Instruction Set Introduction
Table 6-21. Conditional Register Transfer Instructions
Data ALU Transfer
Operation
Source
Tcc DD
A
B
DD
A
B
Note: The Tcc instruction does not allow the following condition codes: HI, LS, NN, and NR.
Operation
IMPY(16)
MAC
MACR
MPY
6-20
AGU Transfer
Destination Source
F (No transfer)
B (No transfer)
A (No transfer)
F R0
B R0
A R0
Table 6-22. Data ALU Multiply Instructions
Operands C
Y1,X0,FDD
Y0,X0,FDD
Y1,Y0,FDD
Y0,Y0,FDD
A1,Y0,FDD
B1,Y1,FDD
(±)Y1,X0,FDD
(±)Y0,X0,FDD
(±)Y1,Y0,FDD
(±)Y0,Y0,FDD
(±)A1,Y0,FDD
(±)B1,Y1,FDD
(±)Y1,X0,FDD
(±)Y0,X0,FDD
(±)Y1,Y0,FDD
(±)Y0,Y0,FDD
(±)A1,Y0,FDD
(±)B1,Y1,FDD
(±)Y1,X0,FDD
(±)Y0,X0,FDD
(±)Y1,Y0,FDD
(±)Y0,Y0,FDD
(±)A1,Y0,FDD
(±)B1,Y1,FDD
DSP56800 Family Manual
C W
Destination
2 1
2 1
2 1
R1 2 1
R1 2 1
R1 2 1
W
2 1 Integer 16x16 multiply with 16-bit result
When the destination is an accumulator F, the
F0 portion is unchanged by the instruction
Note: Assembler also accepts first two oper-
ands when they are specified in opposite order
2 1 Fractional multiply accumulate; multiplication
result optionally negated before accumulation
Note: Assembler also accepts first two oper-
ands when they are specified in opposite orde
2 1 Fractional MAC with round, multiplication result
optionally negated before addition
Note: Assembler also accepts first two oper-
ands when they are specified in opposite orde
2 1 Fractional multiply where one operand is
optionally negated before multiplication
Note: Assembler also accepts first two oper-
ands when they are specified in opposite order
Comments
Conditionally transfer one
register
Conditionally transfer one
data ALU register and one
AGU register
Comments