Table A-12 Parallel Move Timing - Motorola DSP56800 Manual

Instruction
Mnemonic
DEC(W) 1+ea
DIV 1
DO 2
ENDDO 1
EOR 1
EORC 2+ea
ILLEGAL 1
IMPY(16) 1
INC(W) 1+ea
Jcc 2
JMP 2
JSR 2
LEA 1+ea
LSL 1
LSLL 1
LSR 1
1. This MOVE applies only to the case where two reads are performed in parallel from the X memory.
2. The STOP instruction disables the internal clock oscillator. After the clock is turned on, an internal
counter counts 65,536 cycles before enabling the clock to the internal DSP circuits.
3. The WAIT instruction takes a minimum of 16 cycles to execute when an internal interrupt is pending at
the time the WAIT instruction is executed.
Parallel Move Operation
No parallel data move
X: (X memory move)
X: X: (XX memory move)
Table A-11. Instruction Timing Summary (Continued)
Clock Cycles
Words
2+(ea or mv)
2
6
2
2
4+mvb
4
2
2+(ea or mv)
4+jx
6+jx
8+jx
2+ea
2
2
2
Table A-12. Parallel Move Timing
Instruction Set Details
Instruction
Mnemonic
Words
REP 1
RND 1
ROL 1
ROR 1
RTI 1
RTS 1
SBC 1
2
STOP 1
SUB 1+ea
SWI 1
Tcc 1
TFR 1
TST 1
TSTW 1
3
WAIT 1
+ mv Words
0
0
0
Clock Cycles
6
2+mv
2
2
10+rx
10+rx
2
n/a
2+(ea or mv)
8
2
2+mv
2+mv
2+tst
n/a
+mv Cycles
0
ax
axx
A-19