Motorola DSP56800 Manual page 15

List of Figures
Figure 1-1 DSP56800-Based DSP Microcontroller Chip. . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Figure 1-2 DSP56800 Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
Figure 1-3 Example of Chip Built Around the DSP56800 Core . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 1-4 Analog Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Figure 1-5 Digital Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Figure 1-6 Mapping DSP Algorithms into Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Figure 2-1 DSP56800 Core Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2 DSP56800 Memory Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Figure 2-3 Sample DSP56800-Family Chip Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Figure 2-4 DSP56800 Core Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Figure 3-1 Data ALU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Figure 3-2 Data ALU Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Figure 3-3 Right and Left Shifts Through the Multi-Bit Shifting Unit . . . . . . . . . . . . . . . . 3-6
Figure 3-4 Writing the Accumulator Extension Registers (F2) . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3-5 Reading the Accumulator Extension Registers (F2). . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 3-6 Writing the Accumulator by Portions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 3-7 Writing the Accumulator as a Whole . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Figure 3-8 Bit Weightings and Operand Alignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
Figure 3-9 Word-Sized Integer Addition Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
Figure 3-10 Comparison of Integer and Fractional Multiplication . . . . . . . . . . . . . . . . . . . 3-19
Figure 3-11 MPY Operation-Fractional Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Figure 3-12 Integer Multiplication (IMPY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
Figure 3-13 Single-Precision Times Double-Precision Signed Multiplication . . . . . . . . . . 3-24
Figure 3-14 Example of Saturation Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
Figure 3-15 Convergent Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-31
Figure 3-16 Two's-Complement Rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
Figure 4-1 Address Generation Unit Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-2 Address Generation Unit Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
Figure 4-3 Address Register Indirect: No Update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Figure 4-4 Address Register Indirect: Post-Increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Figure 4-5 Address Register Indirect: Post-Decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
Figure 4-6 Address Register Indirect: Post-Update by Offset N . . . . . . . . . . . . . . . . . . . . 4-13
Figure 4-7 Address Register Indirect: Indexed by Offset N. . . . . . . . . . . . . . . . . . . . . . . . 4-14
Figure 4-8 Address Register Indirect: Indexed by Short Displacement . . . . . . . . . . . . . . . 4-15
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