8.2.7 Special-Purpose MOVE Instruction
The special-purpose MOVE instruction table indicates the number of clock periods needed
for the processor to fetch, calculate, and perform the special-purpose MOVE operation on
the control registers or specified effective address. The total number of clock cycles is
outside the parentheses, the number of read, prefetch, and write cycles is given inside the
parentheses as (r/p/w). These cycles are included in the total clock cycle number.
Instruction
EXG
MOVEC
MOVEC
MOVE
†
MOVE
*
MOVE
*
MOVE
‡
MOVEM
‡
MOVEM
MOVEP.W
MOVEP.L
MOVEP.W
MOVEP.L
‡
MOVES
‡
MOVES
MOVE
SWAP
n—Number of Registers to Transfer
RL—Register List
*
Add Fetch Effective Address Time
†Add Calculate Effective Address Time
‡Add Calculate Immediate Address Time
MOTOROLA
Ry,Rx
Cr,Rn
Rn,Cr
PSW,Rn
PSW,Mem
EA,CCR
EA,SR
EA,RL
RL,EA
Dn,(d
,An)
16
Dn,(d
,An)
16
(d
,An),Dn
16
(d
,An),Dn
16
EA,Rn
Rn,EA
USP
Rx,Ry
M68020 USER'S MANUAL
Best Case
Cache Case
0(0/0/0)
2(0/0/0)
3(0/0/0)
6(0/0/0)
9(0/0/0)
12(0/0/0)
1(0/0/0)
4(0/0/0)
5(0/0/1)
5(0/0/1)
4(0/0/0)
4(0/0/0)
8(0/0/0)
8(0/0/0)
8 + 4n (n/0/0)
8 + 4n (n/0/0)
4 + 3n (0/0/n)
4 + 3n (0/0/n)
8(0/0/2)
11(0/0/2)
14(0/0/4)
17(0/0/4)
10(2/0/0)
12(2/0/0)
16(4/0/0)
18(4/0/0)
7(1/0/0)
7(1/0/0)
5(0/0/1)
5(0/0/1)
0(0/0/0)
2(0/0/0)
1(0/0/0)
4(0/0/0)
Worst Case
3(0/1/0)
7(0/1/0)
13(0/1/0)
5(0/1/0)
7(0/1/1)
5(0/1/0)
11(0/2/0)
9 + 4n (n/1/0)
5 + 3n (0/1/n)
11(0/1/2)
17(0/1/4)
12(2/1/0)
18(4/1/0)
8(1/1/0)
7(0/1/1)
3(0/1/0)
4(0/1/0)
8- 29