Table of Contents
Advertisement
General-Purpose Timer Registers
The maximum timer resolution is one system clock cycle (15 nS at 66 MHz). The
4
8
16
maximum period (the reference value is all ones) is 268,435,456 cycles = 2
* 2
* 2
(4 seconds at 66 MHz).
The timer can be configured to count until a reference is reached at which point it can either
start a new time count immediately or continue to run. The free run/restart bit,
TMRn[FRR], selects each mode. Upon reaching the reference value, the TER0 or TER1 bit
is set, and an interrupt is issued if the output reference interrupt enable bit, TMR[ORI], is
set.
Timers 0 and 2 may output a signal on the timer outputs (TOUT0 or TOUT1) when the
reference value is reached, as selected by the output mode bit, TMR[OM]. This signal can
be an active-low pulse or a toggle of the current output, under program control.
The TCRs are used to latch counter values when the corresponding input capture edge
detector detects a defined transition (of TIN0, TIN1, URT0_RxD, or URT1_RxD). The type
of transition triggering the capture is selected by the capture edge bits, TMR[CE].A capture
or reference event sets the TER bit and generates a maskable interrupt.
15.3 General-Purpose Timer Registers
The following sections describe the timer registers.
15.3.1 Timer Mode Registers (TMR0–TMR3)
The TMRs, Table 15-2, have fields for choosing a prescaler, a clock edge, and other
parameters.
15
8
7
6
5
4
3
2
1
0
1
Field
PRESCALER (PS)
CE
OM
ORI
FRR
CLK
RST
Reset
0000_0000_0000_0000
R/W
Read/Write
Addr
MBAR + 0x200 (TMR0); 0x220 (TMR1); 0x240 (TMR2); 0x260 (TMR3)
1
Not implemented (reserved) in TMR2 and TMR3.
Figure 15-2. Timer Mode Registers (TMR0–TMR3)
TMRn fields are described in Table 15-1.
Chapter 15. Timer Module
15-3
Advertisement
Table of Contents
