Word Write Access Bus Cycle Terminated With Tea Timing - Motorola M68060 User Manual

Bus Operation
MISCELLANEOUS
ATTRIBUTES
Figure 7-37. Word Write Access Bus Cycle Terminated with TEA Timing
implemented with an external device that latches the write data when a bus error terminates
a write cycle.
7.9.2 Retry Operation
When an external device asserts both the TA and TEA signals during a bus cycle in the
MC68040 acknowledge termination mode or if an external device asserts TRA with TEA
negated during a bus cycle in the native-MC68060 acknowledge termination mode, the pro-
cessor enters the retry bus operation sequence. The processor terminates the bus cycle and
immediately retries the bus cycle using the same access information (address and transfer
attributes). However, if the bus cycle was a cache push operation and the bus is arbitrated
away from the MC68060 before the retry operation with a snoop access during the arbitra-
tion which invalidates the cache push, the processor does not initiate a retry operation. Fig-
ure 7-39 illustrates a functional timing diagram for a retry of a read bus transfer.
7-48
C1 C2
BCLK
A31–A0
SIZ1
SIZ0
R/W
TS
TIP
SAS
TA
TEA
PRE
D31–D0
DRIVE
WRITE CYCLE
M68060 USER'S MANUAL
C1
WORD
PRE
DRIVE
WRITE STACK
C2
MOTOROLA