Interrupt Acknowledge Bus Cycles; Interrupt Acknowledge Cycle-Terminated Normally - Motorola MC68020 User Manual

FUNCTION
CODE
2 0
BREAKPOINT
1 1 1
ACKNOWLEDGE
ACCESS LEVEL
1 1 1
CONTROL
COPROCESSOR
1 1 1
COMMUNICATION
INTERRUPT
1 1 1
ACKNOWLEDGE
Figure 5-31. MC68020/EC020 CPU Space Address Encoding

5.4.1 Interrupt Acknowledge Bus Cycles

When a peripheral device signals the processor (with the IPL2–IPL0 signals) that the
device requires service and when the internally synchronized value on these signals
indicates a higher priority than the interrupt mask in the status register (or that a transition
has occurred in the case of a level 7 interrupt), the processor makes the interrupt a
pending interrupt. Refer to Section 6 Exception Processing for details on the recognition
of interrupts.
The MC68020/EC020 takes an interrupt exception for a pending interrupt within one
instruction boundary (after processing any other pending exception with a higher priority).
The following paragraphs describe the various kinds of interrupt acknowledge bus cycles
that can be executed as part of interrupt exception processing.
5.4.1.1 INTERRUPT ACKNOWLEDGE CYCLE—TERMINATED NORMALLY. When the
MC68020/EC020 processes an interrupt exception, it performs an interrupt acknowledge
cycle to obtain the number of the vector that contains the starting location of the interrupt
service routine.
Some interrupting devices have programmable vector registers that contain the interrupt
vectors for the routines they use. The following paragraphs describe the interrupt
acknowledge cycle for these devices. Other interrupting conditions or devices cannot
supply a vector number and use the autovector cycle described in 5.4.1.2 Autovector
Interrupt Acknowledge Cycle.
MOTOROLA
31 24 23
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
31
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
31
1 1 1 1 1 1 1 1 1 1 1 1
M68020 USER'S MANUAL
ADDRESS BUS
20 19 16 15
0 0 0 0 0 0 0 0 0 0 0
20 19 16 15
0 0 0 0 0 0 0 0 0
20 19 16 15 13 12
CpID 0 0 0 0 0 0 0 0
20 19 16 15
1 1 1 1 1 1 1 1 1
CPU SPACE
TYPE FIELD
5 4 2 1
BKPT # 0 0
7 6
MMU REG
5 4
CP REG
4 3
LEVEL
1 1 1 1 1 1 1
0
0
0
1 0
1
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