Mcc Data Structure Organization - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module

27.2 MCC Data Structure Organization

Each MCC uses the following data structures:
¥ Global MCC parameters (common to all the 128 channels) placed in the DPR from
the offset (relative to the DPR base address) deÞned in Table 13-10.
¥ Channel-speciÞc parameters. Each channel use 64 bytes of speciÞc parameters
placed in the DPR at offset 64*CH_NUM (relative to the DPR base address).
CH_NUM is the channel number (0Ð127 for MCC1 and 128Ð255 for MCC2).
Channel-speciÞc parameters are described in Section 27.6, ÒChannel-SpeciÞc
HDLC Parameters,Ó and Section 27.7, ÒChannel-SpeciÞc Transparent Parameters.Ó
Note that the DPR memory corresponding to the inactive channels can be used for
other purposes.
¥ Channel extra parameters. Each channel use 8 bytes of extra parameters placed in
the DPR at offset XTRABASE + 8*CH_NUM (relative to the DPR base address).
XTRABASE is one of the global MCC parameters.
Channel extra parameters are described in Section 27.4, ÒChannel Extra
Parameters.Ó Note that the DPR memory corresponding to the inactive channels can
be used for other purposes.
¥ Super channel table (used only if super channels are deÞned). This table is placed in
the DPR from the offset SCTPBASE (relative to the DPR base address).
SCTPBASE is one of the global MCC parameters. The super channel tale is
described in Section 27.5, ÒSuper-Channel Table.Ó
¥ BD tables placed in the external memory. All the BD tables associated with one
MCC must reside in a 512-KByte segment. The absolute base addresses of a channel
BD table is MCCBASE + 8*RBASE (for the receiver) and MCCBASE + 8*TBASE
(for the transmitter). MCCBASE is one of the global MCC parameters and RBASE/
TBASE are channel extra parameters. Each BD table is a circular queue. One BD
includes status bits, start address and length of a data buffer. Figure 27-1 shows the
BD structure for one MCC.
¥ Circular interrupt tables placed in the external memory. There is one table for the
transmitter interrupts (base address TINTBASE) and between one and four tables
for receiver interrupts (base address RINTBASE0ÐRINTBASE4). TINTBASE and
RINTBASE0ÐRINTBASE4 are global MCC parameters.
¥ Three registers (MCCE, MCCM, and MCCF) at described in Section 27.10.1,
ÒMCC Event Register (MCCE)/Mask Register (MCCM),Ó and Section 27.8, ÒMCC
ConÞguration Registers (MCCFx).Ó
27-2 MPC8260 PowerQUICC II UserÕs Manual MOTOROLA