Table of Contents
Advertisement
15.4.13 Interrupt Edge Detection Clear Register (IREDC)
31
15
Reserved
Bit
Mnemonic
Field Name
⎯
31:9
8
EDCE0
Edge Detection
Clear Enable 0
⎯
7:4
3:0
EDCS0
Edge Detection
Clear Source 0
Reserved
9
8
EDCE0
RW1C
0
⎯
Reserved
Edge Detection Clear Enable 0 (Default: 0)
Clears edge detection of interrupts specified by the EDCS0 field.
0: Does not clear.
1: Clears.
Value always becomes "0" when this bit is read.
⎯
Reserved
Edge Detection Clear Source 0 (Default: 0x0)
These bits specify the interrupt source to be cleared.
1111: Reserved
1110: Reserved
1101: Reserved
1100: Reserved
1011: Reserved
1010: Reserved
1001: Reserved
1000: Reserved
0111: External INT [5] interrupt
0110: External INT [4] interrupt
0101: External INT [3] interrupt
0100: External INT [2] interrupt
0011: External INT [1] interrupt
0010: External INT [0] interrupt
0001: Reserved
0000: Reserved
Figure 15.4.13 Interrupt Status Control Register
15-33
Chapter 15 Interrupt Controller
0xF660
7
4
3
Reserved
Explanation
16
: Type
: Default
0
EDCS0
R/W
: Type
0000
: Default
Read/Write
⎯
R/W1C
⎯
R/W
Advertisement
Table of Contents
