Dma/Interrupt Control Register 0 (Sidicr0) 0Xf304 (Ch. 0) Dma/Interrupt Control Register 1 (Sidicr1) 0Xf404 (Ch. 1) - Toshiba TX49 TMPR4937 Manual

11.4.2 DMA/Interrupt Control Register 0 (SIDICR0)
DMA/Interrupt Control Register 1 (SIDICR1)
These registers use either DMA or interrupts to execute the Host Interface.
31
15 14 13 12
TDE RDE TIE RIE
R/W R/W R/W R/W
0 0 0 0
Bit Mnemonic Field Name
31:16 Reserved
Transmit DMA
15 TDE
Transfer Enable
Receive DMA
14 RDE
Transfer Enable
13 TIE Transmit Data
Empty Interrupt
Enable
Reception Data
12 RIE
Full Interrupt
Enable
11 SPIE Reception Error
Interrupt Enable
CTSS Active
10:9 CTSAC
Condition
8:6 Reserved
Reserved
11 10 9 8
SPIE CTSAC Reserved
R/W R/W
0 00
Transmit DMA Enable (Default: 0)
This field sets whether to use DMA in the method for writing transmission
data to the Transmit FIFO.
0: Do not use DMA.
1: Use DMA.
Receive DMA Enable (Default: 0)
This field sets whether to use DMA in the method for reading reception
data from the Receive FIFO.
0: Do not use DMA.
1: Use DMA.
Transmit Data Empty Interrupt Enable (Default: 0)
When there is open space in the Transmit FIFO, this field sets whether to
signal an interrupt. Set "0" when in the DMA Transmit mode (TDE = 1).
0: Do not signal an interrupt when there is open space in the Transmit
FIFO.
1: Signal an interrupt when there is open space in the Transmit FIFO.
Receive Data Full Interrupt Enable (Default: 0)
This field sets whether to signal interrupts when reception data is full
(SIDISRn.RDIS = 1) or a reception time out (SIDISRn.TOUT = 1) occurs.
Set to "0" when in the DMA Receive mode (RDE = 1).
0: Do not signal interrupts when reception data is full/reception time out
occurred.
1: Signal interrupts when reception data is full/reception time out occurred.
Receive Data Error Interrupt Enable (Default: 0)
This field sets whether to signal interrupts when a reception error (Frame
Error, Parity Error, Overrun Error) occurs (SIDISR.ERI = 1).
0: Do not signal reception error interrupts.
1: Signal reception error interrupts.
CTSS Active Condition (Default: 00)
This field specifies status change interrupt request conditions using the
CTS Status (CTSS) of the Status Change Interrupt Status Register.
00: Do not detect CTS signal changes.
01: Rising edge of the CTS pin
10: Falling edge of the CTS pin
11: Both edges of the CTS pin
Figure 11.4.2 DMA/Interrupt Control Register (1/2)
11-15
Chapter 11 Serial I/O Port
0xF304 (Ch. 0)
0xF404 (Ch. 1)
6 5
STIE
R/W
000000
Description
16
: Type
: Initial value
0
: Type
: Initial value
Read/Write
⎯
R/W
R/W
R/W
R/W
R/W
R/W
⎯