Dma Channel Control Register (Dm0Ccrn, Dm1Ccrn) - Toshiba TX49 TMPR4937 Manual

8.4.2

DMA Channel Control Register (DM0CCRn, DM1CCRn)

Offset address: DMAC0 0xB030 (ch. 0) / 0xB070 (ch. 1) / 0xB0B0 (ch. 2) / 0xB0F0 (ch. 3)
63
47
31 30 29 28
Reserved
IMMCHN
USEXFSZ
R/W R/W
0 0
15 13 12
STLTIME/INTRQD
INTENE INTENC INTENT CHNEN XFACT
R/W R/W
000 0
Bit Mnemonic Field Name
63:32 Reserved
29 IMMCHN Immediate Chain
Transfer Set Size
28 USEXFSZ
Mode
27 LE Little Endian
DMAC1 0xB830 (ch. 0) / 0xB870 (ch.1 ) / 0xB8B0 (ch. 2) / 0xB8F0 (ch. 3)
Reserved
Reserved
27 26 25 24
LE
DBINH SBINH CHRST
RVBYTE ACKPOL
R/W R/W R/W R/W
⎯
0 0 1
11 10 9 8
R/W R/W R R/W
0 0 0 0
Immediate Chain (Default: 0)
Always set this bit to "1".
Use Transfer Set Size (Default: 0)
Selects the DMA channel operation mode during Burst DMA transfer.
Refer to "8.3.7.2 Burst Transfer During Single Address Transfer" and
"8.3.8.2 Burst Transfer During Dual Address Transfer" for more
information.
1: The DMA Controller always transfers the amount of data set in
DMCCRn.XFSZ for each bus operation. Since alignment to the
boundary of the DMCCRn.XFSZ in the address is not forced when in
this mode, transfers that exceed 32-double-word boundaries are divided
into two operations.
0: The DMA Controller calculates the transfer size so the address set in
DMSARn and DMDARn (only during Dual Address transfer) can be
aligned to the boundary of the size set in DMCCRn.XFSZ, then
transfers data according to that size.
Note: In Dual Address Transfer mode, programming this bit to 1 is valid
only when both the contents of the DMSARn and the DMDARn are
on doubleword boundaries and the contents of the DMCNTRn is a
multiple of eight bytes.
Little Endian (Default: value that is the opposite of the G-Bus Endian
(CCFG.ENDIAN)
This bit sets the Endian of the channel. Please use the default value as is.
1: Channel operates in the Little Endian mode
0: Channel operates in the Big Endian mode
Figure 8.4.2 DMA Channel Control Register (1/4)
8-27
Chapter 8 DMA Controller
23 22 21 20 19
REQPL EGREQ CHDN
R/W R/W R/W R/W R/W
0 0 0 0
7 6 5 4
Reserved XFSZ
SMPCHN
R/W R/W
0 000
Description
48
: Type
: Initial value
32
: Type
: Initial value
18 17 16
DNCTL
EXTRQ
: Type
R/W R/W
: Initial value
0 00 0
2 1 0
MEMIO SNGAD
: Type
R/W R/W
: Initial value
0 0
Read/Write
⎯
R/W
R/W
R/W