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Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series.
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Advertisement

Hitachi 16-Bit Single-Chip Microcomputer
ADE-602-207C
Rev. 4.0
9/20/02
Hitachi, Ltd.
H8S/2646 Series
H8S/2646
HD6432646
H8S/2645
HD6432645
H8S/2647
HD6432647
H8S/2648
HD6432648
H8S/2646R F-ZTAT™
HD64F2646R
H8S/2648R F-ZTAT™
HD64F2648R
Hardware Manual

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   Summary of Contents for Hitachi H8S/2646

  • Page 1

    Hitachi 16-Bit Single-Chip Microcomputer H8S/2646 Series H8S/2646 HD6432646 H8S/2645 HD6432645 H8S/2647 HD6432647 H8S/2648 HD6432648 H8S/2646R F-ZTAT™ HD64F2646R H8S/2648R F-ZTAT™ HD64F2648R Hardware Manual ADE-602-207C Rev. 4.0 9/20/02 Hitachi, Ltd.

  • Page 2

    Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.

  • Page 3

    General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.

  • Page 5

    Note: * F-ZTAT™ is a trademark of Hitachi, Ltd. Target Users: This manual was written for users who will be using the H8S/2646 Series in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.

  • Page 6

    H8S/2646 Series manuals: Manual Title ADE No. H8S/2646 Series Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083 Users manuals for development tools: Manual Title ADE No. C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual ADE-702-247 Simulator Debugger (for Windows) Users Manual...

  • Page 7

    List of Items Revised or Added for This Version Section Page Description 2.10.2 Caution to 76, 77 Newly added observe when using The BSET, BCLR, BNOT, BST and BIST instructions read data in a unit of byte, bit manipulation then, after bit manipulation, they write data in a unit of byte. Therefore, caution instructions must be exercised when executing any of these instructions for registers and ports that include write-only bits.

  • Page 8

    Section Page Description 9.13.2 Register Part F Data Register (PFDR) Configuration — PF6DR PF5DR PF4DR PF3DR PF2DR — PF0DR Initial value : undefined — 2nd line changed as follows PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF6 to PF2, PF0).

  • Page 9

    Section Page Description 15.3.2 Initialization 565 to Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing after Hardware setting must be made each time a CAN node begins communication. The baud rate and bit timing settings are made in the bit configuration register (BCR).

  • Page 10

    Section Page Description 15.3.2 Initialization 565 to Example: With a 1 Mb/s baud rate and a 20 MHz input clock: after Hardware 20 MHz Reset 1 Mb/s = 2 × (0 + 1) × (3 + 4 + 3) Bit Rate and Bit Set Values Actual Values Timing Settings...

  • Page 11

    Section Page Description Error warning interrupt (TEC ≥ 96) 15.3.7 Interrupt IRR3 Interface Error warning interrupt (REC ≥ 96) IRR4 Table 15-5 HCAN IRR7 Overload frame transmission interrupt Interrupt Sources 15.5 Usage Notes Newly added 9. HTxD pin output HTxD pin output in error passive state in error passive state If the HRxD pin becomes fixed at 1 during message transmission or 10.

  • Page 12

    Section Page Description 23.1 Absolute Input voltage (OSC1, OSC2) –0.3 +3.5 Maximum Ratings lnput voltage (XTAL, EXTAL) –0.3 to A +0.3 Input voltage (ports 4 and 9) –0.3 to AV +0.3 Table 23-1 Input voltage (ports A, B, C, D, E, –0.3 to LPV +0.3 Absolute Maximum...

  • Page 13

    Section Page Description B.2 Functions TXACK—Transmit Acknowledge Register H'F80A HCAN TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 — Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* — TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial value R/(W)* R/(W)* R/(W)* R/(W)*...

  • Page 14

    Section Page Description B.2 Functions RFPR—Remote Request Register H'F810 HCAN RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 Initial value R/(W)* R/(W)* R/(W)* R/(W)*...

  • Page 15

    Section Page Description B.2 Functions UMSR—Unread Message Status Register H'F81A HCAN UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 Initial value R/(W)* R/(W)* R/(W)*...

  • Page 17: Table Of Contents

    Contents Section 1 Overview..................1 Overview..........................Internal Block Diagram...................... Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions in Each Operating Mode..............10 1.3.3 Pin Functions ......................20 Section 2 CPU....................27 Overview..........................27 2.1.1 Features ......................... 27 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU........28 2.1.3 Differences from H8/300 CPU ................

  • Page 18: Table Of Contents

    Basic Timing........................71 2.9.1 Overview....................... 71 2.9.2 On-Chip Memory (ROM, RAM)................71 2.9.3 On-Chip Supporting Module Access Timing ............73 2.9.4 On-Chip HCAN Module Access Timing.............. 75 2.9.5 External Address Space Access Timing ............... 76 2.10 Usage Note ......................... 76 2.10.1 TAS Instruction ....................

  • Page 19: Table Of Contents

    Section 5 Interrupt Controller ................101 Overview..........................101 5.1.1 Features ......................... 101 5.1.2 Block Diagram...................... 102 5.1.3 Pin Configuration....................103 5.1.4 Register Configuration..................103 Register Descriptions ......................104 5.2.1 System Control Register (SYSCR)............... 104 5.2.2 Interrupt Priority Registers A to H, J, K, M (IPRA to IPRH, IPRJ, IPRK, IPRM)..............

  • Page 20: Table Of Contents

    6.2.3 Break Control Register A (BCRA) ............... 132 6.2.4 Break Control Register B (BCRB) ............... 134 6.2.5 Module Stop Control Register C (MSTPCRC) ............ 134 Operation..........................135 6.3.1 PC Break Interrupt Due to Instruction Fetch............135 6.3.2 PC Break Interrupt Due to Data Access ............... 135 6.3.3 Notes on PC Break Interrupt Handling..............

  • Page 21: Table Of Contents

    Write Data Buffer Function ....................178 Bus Arbitration........................179 7.8.1 Overview ......................179 7.8.2 Operation ......................179 7.8.3 Bus Transfer Timing ..................... 179 Resets and the Bus Controller.................... 180 Section 8 Data Transfer Controller (DTC) ............181 Overview..........................181 8.1.1 Features ......................... 181 8.1.2 Block Diagram......................

  • Page 22: Table Of Contents

    9.2.3 Pin Functions ......................224 Port 2..........................232 9.3.1 Overview....................... 232 9.3.2 Register Configuration..................232 9.3.3 Pin Functions ......................234 Port 3..........................242 9.4.1 Overview....................... 242 9.4.2 Register Configuration..................242 9.4.3 Pin Functions ......................245 Port 4..........................247 9.5.1 Overview....................... 247 9.5.2 Register Configuration..................

  • Page 23: Table Of Contents

    9.12.2 Register Configuration..................277 9.12.3 Pin Functions ......................279 9.12.4 MOS Input Pull-Up Function................279 9.13 Port F..........................281 9.13.1 Overview....................... 281 9.13.2 Register Configuration..................282 9.13.3 Pin Functions ......................284 9.14 Port H ..........................287 9.14.1 Overview....................... 287 9.14.2 Register Configuration..................287 9.14.3 Pin Functions ......................

  • Page 24: Table Of Contents

    10.4.3 Synchronous Operation ..................345 10.4.4 Buffer Operation ....................347 10.4.5 Cascaded Operation ....................351 10.4.6 PWM Modes ......................353 10.4.7 Phase Counting Mode ................... 358 10.5 Interrupts ..........................365 10.5.1 Interrupt Sources and Priorities ................365 10.5.2 DTC Activation ....................367 10.5.3 A/D Converter Activation..................

  • Page 25: Table Of Contents

    12.1.4 Register Configuration..................416 12.2 Register Descriptions ......................417 12.2.1 Timer Counter (TCNT)..................417 12.2.2 Timer Control/Status Register (TCSR) ..............417 12.2.3 Reset Control/Status Register (RSTCSR) ............422 12.2.4 Notes on Register Access..................423 12.3 Operation..........................425 12.3.1 Watchdog Timer Operation .................. 425 12.3.2 Interval Timer Operation ..................

  • Page 26: Table Of Contents

    14.3.6 Data Transfer Operations..................518 14.3.7 Operation in GSM Mode ..................525 14.3.8 Operation in Block Transfer Mode ............... 526 14.4 Usage Notes ........................527 Section 15 Hitachi Controller Area Network (HCAN) ........531 15.1 Overview..........................531 15.1.1 Features ......................... 531 15.1.2 Block Diagram...................... 532 15.1.3 Pin Configuration....................

  • Page 27: Table Of Contents

    15.2.15 Transmit Error Counter (TEC)................554 15.2.16 Unread Message Status Register (UMSR)............555 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) ........... 556 15.2.18 Message Control (MC0 to MC15)................ 557 15.2.19 Message Data (MD0 to MD15) ................561 15.2.20 Module Stop Control Register C (MSTPCRC) ............ 561 15.3 Operation..........................

  • Page 28: Table Of Contents

    17.1.4 Register Configuration..................615 17.2 Register Descriptions ......................616 17.2.1 PWM Control Registers 1 and 2 (PWCR1, PWCR2)........... 616 17.2.2 PWM Output Control Registers 1 and 2 (PWOCR1, PWOCR2)......617 17.2.3 PWM Polarity Registers 1 and 2 (PWPR1, PWPR2) ........... 618 17.2.4 PWM Counters 1 and 2 (PWCNT1, PWCNT2) ...........

  • Page 29: Table Of Contents

    19.3 Operation..........................655 19.4 Usage Notes ........................655 Section 20 ROM....................657 20.1 Features ..........................657 20.2 Overview..........................658 20.2.1 Block Diagram...................... 658 20.2.2 Mode Transitions ....................659 20.2.3 On-Board Programming Modes................660 20.2.4 Flash Memory Emulation in RAM ............... 662 20.2.5 Differences between Boot Mode and User Program Mode........

  • Page 30: Table Of Contents

    20.11.8 Programmer Mode Transition Time ..............707 20.11.9 Notes on Memory Programming ................708 20.12 Flash Memory and Power-Down States ................709 20.12.1 Notes on Power-Down States ................709 20.13 Flash Memory Programming and Erasing Precautions............710 Section 21 Clock Pulse Generator ..............715 21.1 Overview..........................

  • Page 31: Table Of Contents

    22.6.5 Usage Notes ......................744 22.7 Hardware Standby Mode ....................745 22.7.1 Hardware Standby Mode ..................745 22.7.2 Hardware Standby Mode Timing................746 22.8 Watch Mode ........................746 22.8.1 Watch Mode......................746 22.8.2 Exiting Watch Mode ..................... 747 22.8.3 Notes ........................747 22.9 Sub-Sleep Mode .........................

  • Page 32: Table Of Contents

    Appendix C I/O Port Block Diagrams............1075 Port 1 Block Diagrams ...................... 1075 Port 2 Block Diagrams ......................1081 Port 3 Block Diagrams ...................... 1083 Port 4 Block Diagram ....................... 1090 Port 5 Block Diagrams ...................... 1091 Port 9 Block Diagram ....................... 1095 Port A Block Diagram.......................

  • Page 33: Section 1 Overview

    Section 1 Overview Overview The H8S/2646 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.

  • Page 34

    Table 1-1 Overview Item Specification • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control  Maximum clock rate: 20 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract : 50 ns 16 ×...

  • Page 35

    Segment output pins may be selected four at a time as ports • On-chip power supply division resistor Notes: *1 In the H8S/2646, H8S/2646R, and H8S/2645. *2 In the H8S/2648, H8S/2648R, and H8S/2647. • 92 I/O pins, 16 input-only pins...

  • Page 36

    2 kbytes H8S/2647 • Seven external interrupt pins (NMI, IRQ0 to IRQ5) Interrupt controller • Internal interrupt sources  43 (H8S/2646, H8S/2646R, H8S/2645)  47 (H8S/2648, H8S/2648R, H8S/2647) • Eight priority levels settable Power-down states • Medium-speed mode • Sleep mode •...

  • Page 37

    Item Specification Product lineup Model Name Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Packages HD6432646 HD64F2646R 128 k/4 k FP-144J HD6432645 — 64 k/2 k FP-144G HD6432648 HD64F2648R 128 k/4 k FP-144J HD6432647 — 64 k/2 k FP-144G The HD64F2646R and HD64F2648R use an FP-144J package.

  • Page 38: Internal Block Diagram

    P93/AN11 P92/AN10 P91/AN9 Port 1 Port H Port J Port 4 P90/AN8 Notes: *1 Flash memory version only. *2 The FWE pin is for compatibility with the flash memory version. Figure 1-1 (1) H8S/2646, H8S/2646R, and H8S/2645 Internal Block Diagram...

  • Page 39

    Port D Port E PA7/A23/SEG40 PA6/A22/SEG39 OSC2 PA5/A21/SEG38 OSC1 PA4/A20/SEG37 EXTAL PA3/A19/COM4 XTAL PA2/A18/COM3 PLLCAP PA1/A17/COM2 H8S/2600 CPU PLLVSS PA0/A16/COM1 STBY PB7/A15/SEG32 PB6/A14/SEG31 PB5/A13/SEG30 PB4/A12/SEG29 HTxD Interrupt controller PB3 / A11/SEG28 HRxD PB2/A10/SEG27 PB1/A9/SEG26 PC break controller PF7/ø PB0/A8/SEG25 PF6/AS/SEG36 PC7/A7/SEG24 PF5/RD/SEG35 PC6/A6/SEG23...

  • Page 40: Pin Description

    Pin Description 1.3.1 Pin Arrangement Figure 1-2 (1) shows the pin arrangement of the H8S/2646, H8S/2646R, and H8S/2645, and figure 1-2 (2) shows that of the H8S/2648, H8S/2648R, and H8S/2647. HTxD PWMVSS HRxD PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E P20/TIOCA3 PWMVCC P21/TIOCB3...

  • Page 41

    HTxD PWMVSS HRxD PJ7/PWM2H P50/TxD2 PJ6/PWM2G P51/RxD2 PJ5/PWM2F P52/SCK2 PJ4/PWM2E P20/TIOCA3 PWMVCC P21/TIOCB3 PJ3/PWM2D P22/TIOCC3 PJ2/PWM2C P23/TIOCD3 PJ1/PWM2B P25/TIOCB4 PJ0/PWM2A PWMVSS P24/TIOCA4 PH7/PWM1H PH6/PWM1G P27/TIOCB5 PH5/PWM1F PH4/PWM1E P26/TIOCA5 PWMVCC PH3/PWM1D Top View AVCC PH2/PWM1C Vref (FP-144J, FP-144G) PH1/PWM1B P40/AN0 PH0/PWM1A P41/AN1 PWMVSS P42/AN2...

  • Page 42: Pin Functions In Each Operating Mode

    1.3.2 Pin Functions in Each Operating Mode Tablse 1-2 (1) and 1-2 (2) show the pin functions in each of the operating modes. Table 1-2 (1) Pin Functions in Each Operating Mode (H8S/2646, H8S/2646R, H8S/2645) Pin Name Pin No. Mode 4...

  • Page 43

    Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PC6/A6/SEG7 PC6/SEG7 PC7/A7/SEG8 PC7/SEG8 PB0/A8/SEG9 PB0/A8/SEG9 PB0/A8/SEG9 PB0/SEG9 PB1/A9/SEG10 PB1/A9/SEG10 PB1/A9/SEG10 PB1/SEG10 PB2/A10/SEG11 PB2/A10/SEG11 PB2/A10/SEG11 PB2/SEG11 PB3/A11/SEG12 PB3/A11/SEG12 PB3/A11/SEG12 PB3/SEG12 PB4/A12/SEG13 PB4/A12/SEG13 PB4/A12/SEG13 PB4/SEG13 PB5/A13/SEG14 PB5/A13/SEG14 PB5/A13/SEG14 PB5/SEG14 PB6/A14/SEG15 PB6/A14/SEG15 PB6/A14/SEG15...

  • Page 44

    Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PWMVss PWMVss PWMVss PWMVss PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PWMVcc PWMVcc PWMVcc PWMVcc PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ5/PWM2F PJ5/PWM2F PJ5/PWM2F...

  • Page 45

    Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 XTAL XTAL XTAL XTAL EXTAL EXTAL EXTAL EXTAL PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/ADTRG/IRQ3 PF7/φ PF7/φ PF7/φ PF7/φ P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/...

  • Page 46

    Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 AVcc AVcc AVcc AVcc Vref Vref Vref Vref P40/AN0 P40/AN0 P40/AN0 P40/AN0 P41/AN1 P41/AN1 P41/AN1 P41/AN1 P42/AN2 P42/AN2 P42/AN2 P42/AN2 P43/AN3 P43/AN3 P43/AN3...

  • Page 47

    Table 1-2 (2) Pin Functions in Each Operating Mode (H8S/2648, H8S/2648R, H8S/2647) Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PE0/D0/SEG1 PE0/D0/SEG1 PE0/D0/SEG1 PE0/SEG1 PE1/D1/SEG2 PE1/D1/SEG2 PE1/D1/SEG2 PE1/SEG2 PE2/D2/SEG3 PE2/D2/SEG3 PE2/D2/SEG3 PE2/SEG3 PE3/D3/SEG4 PE3/D3/SEG4 PE3/D3/SEG4 PE3/SEG4 PE4/D4/SEG5 PE4/D4/SEG5 PE4/D4/SEG5...

  • Page 48

    Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PC6/A6/SEG23 PC6/SEG23 PC7/A7/SEG24 PC7/SEG24 PB0/A8/SEG25 PB0/A8/SEG25 PB0/A8/SEG25 PB0/SEG25 PB1/A9/SEG26 PB1/A9/SEG26 PB1/A9/SEG26 PB1/SEG26 PB2/A10/SEG27 PB2/A10/SEG27 PB2/A10/SEG27 PB2/SEG27 PB3/A11/SEG28 PB3/A11/SEG28 PB3/A11/SEG28 PB3/SEG28 PB4/A12/SEG29 PB4/A12/SEG29 PB4/A12/SEG29 PB4/SEG29 PB5/A13/SEG30 PB5/A13/SEG30 PB5/A13/SEG30 PB5/SEG30 PB6/A14/SEG31 PB6/A14/SEG31 PB6/A14/SEG31...

  • Page 49

    Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PWMVss PWMVss PWMVss PWMVss PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PWMVcc PWMVcc PWMVcc PWMVcc PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ5/PWM2F PJ5/PWM2F PJ5/PWM2F...

  • Page 50

    Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 XTAL XTAL XTAL XTAL EXTAL EXTAL EXTAL EXTAL PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/ADTRG/IRQ3 PF7/φ PF7/φ PF7/φ PF7/φ P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/...

  • Page 51

    Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 AVcc AVcc AVcc AVcc Vref Vref Vref Vref P40/AN0 P40/AN0 P40/AN0 P40/AN0 P41/AN1 P41/AN1 P41/AN1 P41/AN1 P42/AN2 P42/AN2 P42/AN2 P42/AN2 P43/AN3 P43/AN3 P43/AN3...

  • Page 52: Pin Functions

    1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2646. Table 1-3 Pin Functions Type Symbol Name and Function Power Input Power supply: For connection to the power supply. All Vcc pins should be connected to the system power supply.

  • Page 53

    Mode pins: These pins set the operating mode. control The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2646 Series is operating. Operating Mode —...

  • Page 54

    Type Symbol Name and Function Bus control Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled.

  • Page 55

    Transmit data: Data output pins. communication interface (SCI)/ Smart Card RxD1, RxD0 Input Receive data: Data input pins. interface H8S/2646, SCK1, SCK0 I/O Serial clock: Clock I/O pins. H8S/2646R, The SCK0 output type is NMOS push-pull. H8S/2645 Serial TxD2 to Output Transmit data: Data output pins.

  • Page 56

    Type Symbol Name and Function SEG24 to Output LCD segment output: LCD segment output pins controller/driver SEG1 (H8S/2646, H8S/2646R, H8S/2645) SEG40 to SEG1 (H8S/2648, H8S/2648R, H8S/2647) COM4 to Output LCD common output: LCD common output pins COM1 I/O ports P17 to P10 Port 1: 8-bit I/O pins.

  • Page 57

    Type Symbol Name and Function I/O ports PF7 to PF2, Port F: 7-bit I/O pins. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). PH7 to PH0 Port H: 8-bit I/O pins. Input or output can be designated for each bit by means of the port H data direction register (PHDDR).

  • Page 59: Section 2 Cpu

    Section 2 CPU Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control.

  • Page 60: Differences Between H8s/2600 Cpu And H8s/2000 Cpu

     32 ÷ 16-bit register-register divide : 1000 ns • Two CPU operating modes  Normal mode*  Advanced mode Note: * Not available in the H8S/2646 Series. • Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.

  • Page 61: Differences From H8/300 Cpu

     Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.  Advanced mode supports a maximum 16-Mbyte address space. Note: * Not available in the H8S/2646 Series. • Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.

  • Page 62: Cpu Operating Modes

    Note: * Not available in the H8S/2646 Series. Figure 2-1 CPU Operating Modes (1) Normal Mode (Not Available in the H8S/2646 Series) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed.

  • Page 63

    Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2-2).

  • Page 64

    Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is not pushed onto the stack.

  • Page 65

    Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). For details of the exception vector table, see section 4, Exception Handling.

  • Page 66

    Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When EXR is invalid, it is not pushed onto the stack.

  • Page 67: Address Space

    (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2646 Series H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Note: * Not available in the H8S/2646 Series. Figure 2-6 Memory Map...

  • Page 68: Register Configuration

    Interrupt mask bits Overflow flag CCR: Condition-code register Carry flag Interrupt mask bit MAC: Multiply-accumulate register User bit or interrupt mask bit* Note: * Cannot be used as an interrupt mask bit in the H8S/2646 Series. Figure 2-7 CPU Registers...

  • Page 69: General Registers

    2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).

  • Page 70: Control Registers

    General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. Free area SP (ER7) Stack area Figure 2-9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),...

  • Page 71

    Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions.

  • Page 72: Initial Register Values

    Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, Instruction List. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.

  • Page 73: Data Formats

    Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.

  • Page 74

    Data Type Register Number Data Format Word data Word data Longword data Legend ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-10 General Register Data Formats (cont)

  • Page 75: Memory Data Formats

    2.5.2 Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.

  • Page 76: Instruction Set

    @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. *2 Bcc is the general name for conditional branch instructions. *3 Not available in the H8S/2646 Series. *4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.

  • Page 77: Instructions And Addressing Modes

    2.6.2 Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes...

  • Page 79: Table Of Instructions Classified By Function

    2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs)

  • Page 80

    Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in the H8S/2646 Series. MOVTPE Cannot be used in the H8S/2646 Series. @SP+ → Rn Pops a register from the stack.

  • Page 81

    Type Instruction Size Function Rd ± Rs → Rd, Rd ± #IMM → Rd Arithmetic B/W/L operations Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register.

  • Page 82

    Type Instruction Size Function Rd ÷ Rs → Rd Arithmetic DIVXS operations Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16- bit remainder.

  • Page 83

    Type Instruction Size Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Logic B/W/L operations Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.

  • Page 84

    Type Instruction Size Function 1 → (<bit-No.> of <EAd>) Bit- BSET manipulation Sets a specified bit in a general register or memory instructions operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.

  • Page 85

    Type Instruction Size Function C ⊕ (<bit-No.> of <EAd>) → C Bit- BXOR manipulation Exclusive-ORs the carry flag with a specified bit in a instructions general register or memory operand and stores the result in the carry flag. C ⊕ [¬ (<bit-No.> of <EAd>) ] → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand...

  • Page 86

    Type Instruction Size Function Branch — Branches to a specified address if a specified condition instructions is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨ Z = 0 High C ∨...

  • Page 87

    Type Instruction Size Function System control TRAPA — Starts trap-instruction exception handling. instructions — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR.

  • Page 88: Basic Instruction Formats

    Type Instruction Size Function if R4L ≠ 0 then Block data EEPMOV.B — Repeat @ER5+ → @ER6+ transfer R4L–1 → R4L instruction Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next;...

  • Page 89

    Figure 2-12 shows examples of instruction formats. (1) Operation field only NOP, RTS, etc. (2) Operation field and register fields ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field EA (disp) BRA d:16, etc...

  • Page 90: Addressing Modes And Effective Address Calculation

    Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.

  • Page 91

    8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction 24 bits (@aa:24) address Note: * Not available in the H8S/2646 Series.

  • Page 92

    0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the H8S/2646 Series.

  • Page 93: Effective Address Calculation

    (a) Normal Mode * (b) Advanced Mode Note: * Not available in the H8S/2646 Series. Figure 2-13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address.

  • Page 94

    Table 2-6 Effective Address Calculation...

  • Page 97: Processing States

    Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.

  • Page 98: Reset State

    End of bus request Bus request Program execution state Bus-released state Sleep mode External interrupt request Software standby mode Exception handling state RES= High STBY= High, RES= Low Reset state Hardware standby mode Power-down state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: *1 goes low.

  • Page 99: Exception-handling State

    2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions.

  • Page 100

    (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the reset state when the RES is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address.

  • Page 101

    (b) Interrupt control mode 2 Advanced mode Reserved (24 bits) (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Notes: *1 Ignored when returning. *2 Not available in the H8S/2646 Series. Figure 2-16 Stack Structure after Exception Handling (Examples)

  • Page 102: Program Execution State

    2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU is data transfer controller (DTC).

  • Page 103: Basic Timing

    Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states.

  • Page 104

    Bus cycle ø Address bus Held High High HWR, LWR High Data bus High-impedance state Figure 2-18 Pin States during On-Chip Memory Access...

  • Page 105: On-chip Supporting Module Access Timing

    2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access cycle for the on-chip supporting modules. Figure 2-20 shows the pin states. Bus cycle ø...

  • Page 106

    Bus cycle ø Held Address bus High High HWR, LWR High Data bus High-impedance state Figure 2-20 Pin States during On-Chip Supporting Module Access...

  • Page 107: On-chip Hcan Module Access Timing

    2.9.4 On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access cycle is shown in figures 2-21 and 2-22, and the pin states in figure 2-23.

  • Page 108: External Address Space Access Timing

    Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used.

  • Page 109

    The BCLR instruction can be used to clear the flag of an internal I/O register to 0. In that case, if it is clearly known that the pertinent flag is set to 1 in an interrupt processing routine or other processing, there is no need to read the flag in advance.

  • Page 111: Section 3 Mcu Operating Modes

    3.1.1 Operating Mode Selection The H8S/2646 Series has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0).

  • Page 112

    The H8S/2646 Series can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration...

  • Page 113: System Control Register (syscr)

    3.2.2 System Control Register (SYSCR) MACS — INTM1 INTM0 NMIEG — — RAME Initial value — — SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI, and enables or disenables on-chip RAM.

  • Page 114: Pin Function Control Register (pfcr)

    Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG Description An interrupt is requested at the falling edge of NMI input (Initial value) An interrupt is requested at the rising edge of NMI input Bit 2—...

  • Page 115

    Bit 3 Bit 2 Bit 1 Bit 0 Description A8–A23 address output disabled (Initial value*) A8 address output enabled; A9–A23 address output disabled A8, A9 address output enabled; A10–A23 address output disabled A8–A10 address output enabled; A11–A23 address output disabled A8–A11 address output enabled;...

  • Page 116: Operating Mode Descriptions

    Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals.

  • Page 117

    *: After reset Address Map in Each Operating Mode A address maps of the H8S/2646 Series are shown in figures 3-1 (1) and 3-1 (2). The address space is 16 Mbytes in modes 4 to 7 (advanced modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus...

  • Page 118

    On-chip RAM* On-chip RAM* On-chip RAM H'FFFFFF H'FFFFFF H'FFFFFF Note: * External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3-1 (1) Address Map in Each Operating Mode in the H8S/2646, H8S/2646R, H8S/2648, and H8S/2648R...

  • Page 119

    Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip mode) with on-chip ROM disabled) with on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'00FFFF H'00FFFF H'010000 H'010000 External address space Reserved area Reserved area H'01FFFF H'01FFFF...

  • Page 121: Section 4 Exception Handling

    Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, direct transition, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.

  • Page 122: Exception Handling Operation

    Reset Trace Exception External interrupts: NMI, IRQ5 to IRQ0 sources Internal interrupts: Interrupts from on-chip supporting modules Interrupts 43 sources in the H8S/2646, H8S/2646R, and H8S/2645 47 sources in the H8S/2648, H8S/2648R, and H8S/2647 Trap instruction Figure 4-1 Exception Sources...

  • Page 123

    Table 4-2 Exception Vector Table Vector Address Exception Source Vector Number Advanced Mode Reset H'0000 to H'0003 Reserved for system use H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 Trace H'0014 to H'0017 Direct Transition H'0018 to H'001B External interrupt H'001C to H'001F Trap instruction (4 sources)

  • Page 124: Reset

    Immediately after a reset, interrupt control mode 0 is set. When the RES pin goes from low to high, reset exception handling starts. The H8S/2646 Series can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer.

  • Page 125

    Vector Internal Prefetch of first program fetch processing instruction ø Internal address bus Internal read signal Internal write High signal Internal data (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction Figure 4-2 Reset Sequence (Modes 6 and 7)

  • Page 126: Interrupts After Reset

    Vector Internal Prefetch of first program fetch processing instruction Ø Address bus HWR, LWR High D15 to D0 (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction Note: * 3 program wait states are inserted.

  • Page 127: State Of On-chip Supporting Modules After Reset Release

    4.2.4 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA to MSTPCRD are initialized to H'3F, H'FF, H'FF, and B'11****** , respectively, and all modules except the DTC, enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited.

  • Page 128: Interrupts

    Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and internal sources (43 sources in the H8S/2646, H8S/2646R, and H8S/2645, and 47 sources in the H8S/2648, H8S/2648R, and H8S/2647) in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type.

  • Page 129: Trap Instruction

    Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code.

  • Page 130: Stack Status After Exception Handling

    (a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return. Figure 4-5 (1) Stack Status after Exception Handling (Normal Modes: Not Available in the H8S/2646 Series) Reserved* (24 bits) (24 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return.

  • Page 131: Notes On Use Of The Stack

    Notes on Use of the Stack When accessing word data or longword data, the H8S/2646 Series assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W...

  • Page 133: Section 5 Interrupt Controller

    Overview 5.1.1 Features The H8S/2646 Series controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes  Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR).

  • Page 134: Block Diagram

    5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority ISCR determination Internal interrupt request I2 to I0 SWDTEND to Interrupt controller Legend...

  • Page 135: Pin Configuration

    5.1.3 Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Interrupt Controller Pins Name Symbol Function Nonmaskable interrupt Input Nonmaskable external interrupt; rising or falling edge can be selected IRQ5 to IRQ0 Input External interrupt Maskable external interrupts; rising, falling, or requests 5 to 0 both edges, or level sensing, can be selected 5.1.4...

  • Page 136: Register Descriptions

    Register Descriptions 5.2.1 System Control Register (SYSCR) MACS — INTM1 INTM0 NMIEG — — RAME Initial value — — SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR).

  • Page 137

    Notes: *1 Reserved. These bits are always read as 1 and cannot be modified. *2 In the H8S/2646, H8S/2646R, and H8S/2645 these are reserved bits that are always read as 1 and should only be written with H'7. In the H8S/2648, H8S/2648R, and...

  • Page 138: Irq Enable Register (ier)

    As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.

  • Page 139: Irq Sense Control Registers H And L (iscrh, Iscrl)

    5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH — — — — IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ5 to IRQ0.

  • Page 140: Irq Status Register (isr)

    5.2.5 IRQ Status Register (ISR) — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt requests.

  • Page 141: Interrupt Sources

    There are seven external interrupts: NMI and IRQ5 to IRQ0. Of these, NMI and IRQ5 to IRQ0 can be used to restore the H8S/2646 Series from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.

  • Page 142: Internal Interrupts

    There are 47 sources in the H8S/2648, H8S/2648R, and H8S/2647 and 43 sources in the H8S/2646, H8S/2646R, and H8S/2645 for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts.

  • Page 143

    Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority External H'001C High IRQ0 H'0040 IPRA6 to 4 IRQ1 H'0044 IPRA2 to 0 IRQ2 H'0048 IPRB6 to 4 IRQ3 H'004C IRQ4...

  • Page 144

    Vector Address Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority TGI1A (TGR1A input H'00A0 IPRF2 to 0 High capture/compare match) channel 1 TGI1B (TGR1B input H'00A4 capture/compare match) TCI1V (overflow 1) H'00A8 TCI1U (underflow 1) H'00AC TGI2A (TGR2A input H'00B0 IPRG6 to 4 capture/compare match)

  • Page 145

    — H'01B8 H'01BC Reserved for system use — H'01C0 — H'01FC Notes: *1 Lower 16 bits of the start address. *2 These vectors are used in the H8S/2648, H8S/2648R, and H8S/2647. They are reserved in the H8S/2646, H8S/2646R, and H8S/2645.

  • Page 146: Interrupt Operation

    5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2646 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.

  • Page 147

    Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 Interrupt acceptance control Default priority Interrupt source Vector number determination 8-level mask control I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.

  • Page 148

    8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level.

  • Page 149: Interrupt Control Mode 0

    5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1.

  • Page 150

    Program execution status Interrupt generated? Hold pending IRQ0 IRQ1 HCAN Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0...

  • Page 151: Interrupt Control Mode 2

    5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.

  • Page 152

    Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 Level 1 interrupt? or below? Mask level 5 or below? Mask level 0? Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in...

  • Page 153: Interrupt Exception Handling Sequence

    5.4.4 Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5-7 Interrupt Exception Handling...

  • Page 154: Interrupt Response Times

    5.4.5 Interrupt Response Times The H8S/2646 Series is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high- speed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine.

  • Page 155: Usage Notes

    Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus Internal 2-State 3-State 2-State 3-State Symbol Memory Access Access Access Access Instruction fetch 6+2m Branch address read Stack manipulation Legend m: Number of wait states in an external device access.

  • Page 156: Instructions That Disable Interrupts

    TIER0 write cycle by CPU TCIV exception handling ø Internal TIER0 address address bus Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5-8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.

  • Page 157: Interrupts During Execution Of Eepmov Instruction

    5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle.

  • Page 158: Operation

    Interrupt DTC activation request request vector Selection number circuit Select interrupt signal Control logic Clear signal DTCER Interrupt source On-chip Clear signal clear signal supporting module DTVECR SWDTE CPU interrupt clear signal request vector number Determination of priority I, I2 to I0 Interrupt controller Figure 5-9 Interrupt Control for DTC 5.6.3...

  • Page 159

    Table 5-11 Interrupt Source Selection and Clearing Control Settings Interrupt Source Selection/Clearing Control DTCE DISEL ∆ ∆ ∆ Legend ∆ : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used.

  • Page 161: Section 6 Pc Break Controller (pbc)

    Section 6 PC Break Controller (PBC) Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC: instruction fetch, data read, data write, and data read/write.

  • Page 162

    6.1.2 Block Diagram Figure 6-1 shows a block diagram of the PC break controller. BARA BCRA Mask control Control Comparator logic Match signal Internal address PC break interrupt Access status Control Comparator logic Match signal Mask control BARB BCRB Figure 6-1 Block Diagram of PC Break Controller...

  • Page 163

    6.1.3 Register Configuration Table 6-1 shows the PC break controller registers. Table 6-1 PC Break Controller Registers Initial Value Name Abbreviation Reset Address Break address register A BARA H'XX000000 H'FE00 Break address register B BARB H'XX000000 H'FE04 Break control register A BCRA R/(W) H'00...

  • Page 164: Break Address Register B (barb)

    6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) CMFA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA Initial value Read/Write R/(W)* Note:* Only a 0 may be written to this bit to clear the flag.

  • Page 165

    Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2–BAMRA0): These bits specify which bits of the break address (BAA23–BAA0) set in BARA are to be masked. Bit 5 Bit 4 Bit 3 BAMRA2 BAMRA1 BAMRA0 Description All BARA bits are unmasked and included in break conditions (Initial value) BAA0 (lowest bit) is masked, and not included in break conditions...

  • Page 166: Break Control Register B (bcrb)

    6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.2.5 Module Stop Control Register C (MSTPCRC) MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value Read/Write MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.

  • Page 167

    Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in sections 6.3.1, PC Break Interrupt Due to Instrunction Fetch, and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch 1.

  • Page 168: Notes On Pc Break Interrupt Handling

    2. Satisfaction of break condition  After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. 3. Interrupt handling  After priority determination by the interrupt controller, PC break interrupt exception handling is started.

  • Page 169: Pc Break Operation In Continuous Data Transfer

    After execution of the SLEEP instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (C)). 4.

  • Page 170: When Instruction Execution Is Delayed By One State

    6.3.6 When Instruction Execution is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. 1. When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in on- chip ROM or RAM is always delayed by one state.

  • Page 171: Additional Notes

    6.3.7 Additional Notes 1. When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address.

  • Page 173: Section 7 Bus Controller

    Section 7 Bus Controller Overview The H8S/2646 Series has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.

  • Page 174

    7.1.2 Block Diagram Figure 7-1 shows a block diagram of the bus controller. Internal Area decoder address bus ABWCR External bus control signals ASTCR BCRH BCRL Internal control controller signals Bus mode signal Wait WAIT controller WCRH WCRL CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal...

  • Page 175

    7.1.3 Pin Configuration Table 7-1 summarizes the pins of the bus controller. Table 7-1 Bus Controller Pins Name Symbol Function Address strobe Output Strobe signal indicating that address output on address bus is enabled. Read Output Strobe signal indicating that external space is being read.

  • Page 176

    Register Descriptions 7.2.1 Bus Width Control Register (ABWCR) ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value : Mode 4 Initial value : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access.

  • Page 177

    ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode.

  • Page 178: Wait Control Registers H And L (wcrh, Wcrl)

    7.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode.

  • Page 179

    Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 5 is accessed...

  • Page 180

    WCRL Initial value Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.

  • Page 181

    Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 1 is accessed...

  • Page 182: Bus Control Register H (bcrh)

    7.2.4 Bus Control Register H (BCRH) ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 — — — Initial value BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in software standby mode.

  • Page 183: Bus Control Register L (bcrl)

    Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access.

  • Page 184

    Bit 1—Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write buffer function in the external write cycle. Bit 1 WDBE Description Write data buffer function not used (Initial value) Write data buffer function used Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by means of the WAIT pin.

  • Page 185

    Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1.

  • Page 186: Overview Of Bus Control

    7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 7-2 shows an outline of the memory map. Note: * Not available in the H8S/2646 Series. H'000000 H'0000...

  • Page 187: Bus Specifications

    7.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.

  • Page 188: Memory Interfaces

    7.3.3 Memory Interfaces The H8S/2646 Series memory interfaces comprise a basic bus interface that allows direct connection or ROM, SRAM, and so on, and a burst ROM interface that allows direct connection of burst ROM. The memory interface can be selected independently for each area.

  • Page 189: Interface Specifications For Each Area

    7.3.4 Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (sections 7.4, Basic Bus Interface and 7.5, Burst ROM Interface) should be referred to for further details.

  • Page 190: Basic Bus Interface

    Basic Bus Interface 7.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7-3). 7.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data...

  • Page 191

    16-Bit Access Space: Figure 7-4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions.

  • Page 192: Valid Strobes

    7.4.3 Valid Strobes Table 7-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.

  • Page 193

    7.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 7-5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle ø...

  • Page 194

    8-Bit 3-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle ø...

  • Page 195

    16-Bit 2-State Access Space: Figures 7-7 to 7-9 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.

  • Page 196

    Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Figure 7-8 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)

  • Page 197

    Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Figure 7-9 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)

  • Page 198

    16-Bit 3-State Access Space: Figures 7-10 to 7-12 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.

  • Page 199

    Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Figure 7-11 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)

  • Page 200

    Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Figure 7-12 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)

  • Page 201: Wait Control

    7.4.5 Wait Control When accessing external space, the H8S/2646 Series can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T...

  • Page 202

    Figure 7-13 shows an example of wait state insertion timing. By WAIT pin By program wait ø WAIT Address bus Read Data bus Read data HWR, LWR Write Data bus Write data Note: Downward arrows show the timing of WAIT pin sampling. Figure 7-13 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, 3 program wait state insertion.

  • Page 203: Burst Rom Interface

    Burst ROM Interface 7.5.1 Overview In this LSI, the area 0 external space can be set as burst ROM space and burst ROM interfacing performed. Burst ROM space interfacing allows 16-bit ROM capable of burst access to be accessed at high-speed. The BRSTRM bit of BCRH sets area 0 as burst ROM space.

  • Page 204

    Full access Burst access ø Low address only changes Address bus Data bus Read data Read data Read data Figure 7.14 (a) Example Burst ROM Access Timing (AST0=BRSTS1=1) Full access Burst access ø Low address only changes Address bus Data bus Read data Read data Read data Figure 7.14 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0)

  • Page 205

    7.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the burst ROM interface initial cycle (full access). See section 7.4.5, Wait Control. Wait states cannot be inserted in the burst cycle.

  • Page 206: Idle Cycle

    Idle Cycle 7.6.1 Operation When the H8S/2646 Series accesses external space , it can insert a 1-state idle cycle (T ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on.

  • Page 207

    (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7-16 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.

  • Page 208

    (3) Relationship between Chip Select (CS*) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal*. An example is shown in figure 7-17. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.

  • Page 209: Pin States During Idle Cycles

    7.6.2 Pin States During Idle Cycles Table 7-5 shows the pin states during idle cycles. Table 7-5 Pin States During Idle Cycles Pins Pin State A23 to A0 Content identical to immediately following bus cycle D15 to D0 High impedance High level High level High level...

  • Page 210: Write Data Buffer Function

    Write Data Buffer Function The H8S/2646 Series has a write data buffer function in the external data bus. Using this function enables external writes to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1.

  • Page 211: Bus Arbitration

    7.8.1 Overview The H8S/2646 Series has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.

  • Page 212: Resets And The Bus Controller

    (3 states), a single data transfer, or a register information write (3 states). Resets and the Bus Controller In a reset, the H8S/2646 Series, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued.

  • Page 213: Section 8 Data Transfer Controller (dtc)

    Section 8 Data Transfer Controller (DTC) Overview The H8S/2646 Series includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features • Transfer possible over any number of channels  Transfer information is stored in memory ...

  • Page 214

    8.1.2 Block Diagram Figure 8-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.

  • Page 215

    8.1.3 Register Configuration Table 8-1 summarizes the DTC registers. Table 8-1 DTC Registers Name Abbreviation Initial Value Address DTC mode register A — Undefined — DTC mode register B — Undefined — DTC source address register — Undefined — DTC destination address register —...

  • Page 216

    Register Descriptions 8.2.1 DTC Mode Register A (MRA) Initial value — — — — — — — — *: Undefined MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer.

  • Page 217

    Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 Description Normal mode Repeat mode Block transfer mode — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.

  • Page 218: Dtc Mode Register B (mrb)

    After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2646 Series, and should always be written with 0.

  • Page 219: Dtc Source Address Register (sar)

    8.2.3 DTC Source Address Register (SAR) Initial value — — — — — — — — — — *: Undefined SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 DTC Destination Address Register (DAR) Initial value...

  • Page 220: Dtc Transfer Count Register B (crb)

    In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00.

  • Page 221: Dtc Vector Register (dtvecr)

    Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn Description DTC activation by this interrupt is disabled (Initial value) [Clearing conditions] • When the DISEL bit is 1 and the data transfer has ended • When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended...

  • Page 222: Module Stop Control Register A (mstpcra)

    Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE Description DTC software activation is disabled (Initial value) [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not ended •...

  • Page 223

    Bit 6—Module Stop (MSTPA6): Specifies the DTC module stop mode. Bit 6 MSTPA6 Description DTC module stop mode cleared (Initial value) DTC module stop mode set...

  • Page 224

    Operation 8.3.1 Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels.

  • Page 225

    The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed.

  • Page 226: Activation Sources

    8.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.

  • Page 227: Dtc Vector Table

    The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. Note: * Not available in the H8S/2646 Series. DTC vector Register information...

  • Page 228

    Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE Priority Write to DTVECR Software DTVECR H'0400+ — High (DTVECR [6:0] <<1) IRQ0 External pin H'0420 DTCEA7 IRQ1 H'0422 DTCEA6 IRQ2 H'0424...

  • Page 229

    Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE Priority TGI3A (GR3A compare match/ H'0460 DTCEC5 High input capture) channel 3 TGI3B (GR3B compare match/ H'0462 DTCEC4 input capture) TGI3C (GR3C compare match/ H'0464 DTCEC3 input capture) TGI3D (GR3D compare match/ H'0466 DTCEC2 input capture)

  • Page 230

    110 to 124 H'04DC — H'04FC Notes: *1 DTCE bits with no corresponding interrupt are reserved, and should be written with 0. *2 These vectors are used in the H8S/2648, H8S/2648R, and H8S/2647. They are reserved in the H8S/2646, H8S/2646R, and H8S/2645.

  • Page 231: Location Of Register Information In Address Space

    8.3.4 Location of Register Information in Address Space Figure 8-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas.

  • Page 232: Normal Mode

    8.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode.

  • Page 233: Repeat Mode

    8.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.

  • Page 234: Block Transfer Mode

    8.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.

  • Page 235

    First block · SAR or DAR or · Block area · Transfer Nth block Figure 8-8 Memory Mapping in Block Transfer Mode...

  • Page 236: Chain Transfer

    8.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8-9 shows the memory map for chain transfer.

  • Page 237: Operation Timing

    8.3.9 Operation Timing Figures 8-10 to 8-12 show an example of DTC operation timing. ø DTC activation request request Data transfer Vector read Address Read Write Transfer Transfer information read information write Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ø...

  • Page 238: Number Of Dtc Execution States

    ø DTC activation request request Data transfer Data transfer Vector read Address Read Write Read Write Transfer Transfer Transfer Transfer information information information information read write read write Figure 8-12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for each execution status.

  • Page 239

    Table 8-9 Number of States Required for Each Execution Status Chip Chip On-Chip I/O Object to be Accessed Registers External Devices Bus width Access states Execution Vector read — — — 6+2m 2 status Register — — — — — —...

  • Page 240: Procedures For Using Dtc

    8.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1.

  • Page 241: Examples Of Use Of The Dtc

    8.3.12 Examples of Use of the DTC Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0).

  • Page 242

    Chain Transfer: An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half.

  • Page 243

    Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).

  • Page 244

    Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.

  • Page 245: Section 9 I/o Ports

    Section 9 I/O Ports Overview The H8S/2646 Series has 13 I/O ports (ports 1 to 3, 5 and A to F, H, J, K), and two input-only port (ports 4 and 9). Table 9-1 summarizes the port functions. The pins of each port also have other functions.

  • Page 246

    Table 9-1 (1) Port Functions (H8S/2646, H8S/2646R, H8S/2645) Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port 1 • 8-bit I/O P17/PO15/TIOCB2 TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, port /TCLKD TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2), PPG output pins (PO15 to PO8), and interrupt input •...

  • Page 247

    Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port 5 • 3-bit I/O 3-bit I/O port port Port 9 • 8-bit input A/D converter analog input (AN11 to AN8) and 8-bit input port port P93/AN11 P92/AN10 P91/AN9 P90/AN8 Port A •...

  • Page 248

    Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port D • 8-bit I/O PD7/D15 Data bus I/O 8-bit I/O port port PD6/D14 • Built-in PD5/D13 MOS input PD4/D12 pull-up PD3/D11 PD2/D10 PD1/D9 PD0/D8 Port E • 8-bit I/O PE7/D7 8-bit I/O port in 8-bit bus mode 8-bit I/O port...

  • Page 249

    Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port J • 8-bit I/O PJ7/PWM2H Motor control PWM timer (channel 2) output pins (PWM2A to port PWM2H) and 8-bit I/O port PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E PJ3/PWM2D PJ2/PWM2C PJ1/PWM2B PJ0/PWM2A Port K •...

  • Page 250

    Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port 3 • 8-bit I/O SCI (channels 0, 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1), interrupt input pins (IRQ4, IRQ5), and 8-bit I/O port port • Open-drain P35/SCK1/IRQ5 output P34/RxD1...

  • Page 251

    Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port B • 8-bit I/O PB7/A15/SEG32 LCD segment output (SEG25 to SEG32), LCD segment port address output (A15 to A8), and 8-bit I/O port output (SEG25 PB6/A14/SEG31 to SEG32) and •...

  • Page 252

    Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port F • 7-bit I/O PF7/φ If DDR = 0: input port port If DDR = 1: φ output LCD segment output (SEG34 to SEG36) and LCD segment PF6/AS/SEG36 bus control signals (AS, RD, HWR) output (SEG34 PF5/RD/SEG35...

  • Page 253: Port

    Port 1 9.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and external interrupt pins (IRQ0 and IRQ1). Port 1 pin functions change according to the operating mode.

  • Page 254

    9.2.2 Register Configuration Table 9-2 shows the port 1 register configuration. Table 9-2 Port 1 Registers Name Abbreviation Initial Value Address* Port 1 data direction register P1DDR H'00 H'FE30 Port 1 data register P1DR H'00 H'FF00 Port 1 register PORT1 Undefined H'FFB0 Note: * Lower 16 bits of the address.

  • Page 255

    Port 1 Register (PORT1) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins P17 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR.

  • Page 256

    9.2.3 Pin Functions Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and external interrupt input pins (IRQ0 and IRQ1). Port 1 pin functions are shown in table 9-3.

  • Page 257

    Selection Method and Pin Functions P16/PO14/ The pin function is switched as shown below according to the combination of TIOCA2/ the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 IRQ1 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, and bit P16DDR.

  • Page 258

    Selection Method and Pin Functions P15/PO13/ The pin function is switched as shown below according to the combination of TIOCB1/TCLKC the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.

  • Page 259

    Selection Method and Pin Functions P14/PO12/ The pin function is switched as shown below according to the combination of TIOCA1/IRQ0 the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR.

  • Page 260

    Selection Method and Pin Functions P13/PO11/ The pin function is switched as shown below according to the combination of TIOCD0/TCLKB the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR.

  • Page 261

    Selection Method and Pin Functions P12/PO10/ The pin function is switched as shown below according to the combination of TIOCC0/TCLKA the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR.

  • Page 262

    Selection Method and Pin Functions P11/PO9/TIOCB0 The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, and bits IOB3 to IOB0 in TIOR0H), bit NDER9 in NDERH, and bit P11DDR.

  • Page 263

    Selection Method and Pin Functions P10/PO8/TIOCA0 The pin function is switched as shown below according to the combination of the operating mode, and the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit NDER8 in NDERH, SAE0 bit in DMABCRH, and bit P10DDR.

  • Page 264

    Port 2 9.3.1 Overview Port 2 is an 8-bit I/O port. Port 2 also functions as TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3, TIOCC3, TIOCB3, TIOCA3). The pin functions of port 2 change with the operating mode. Figure 9-2 shows the pin functions for port 2. Port 2 pins (I/O) / TIOCB5 (I/O) (I/O) / TIOCA5 (I/O)

  • Page 265

    Port 2 Data Direction Register (P2DDR) P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : P2DDR is an 8-bit write-only register that specifies whether individual bits are input or output for each of the pins in port 2. It is not possible to read it. An undefined value is returned if an attempt is made to read it.

  • Page 266

    P2DDR and P2DR are initialized if a reset occurs and in the hardware standby mode, so the content of PORT2 is determined by the pin states. The previous states are retained in the software standby mode. 9.3.3 Pin Functions The port 2 pins also function as TPU I/O pins (TIOCB5, TIOCA5, TIOCB4, TIOCA4, TIOCD3, TIOCC3, TIOCB3, TIOCA3).

  • Page 267

    Selection Method and Pin Functions P26/TIOCA5 Switches as follows according to the combinations of the TPU channel 5 setting made using bits MD3 to MD0 of TMDR5, bits IOA3 to IOA0 of TIOR5, and bits CCLR1 and CCLR0 of TCR5, as well as the P26DDR bit. TPU Channel 5 Setting Table Below (1)

  • Page 268

    Selection Method and Pin Functions P25/TIOCB4 Switches as follows according to the combinations of the TPU channel 4 setting made using bits MD3 to MD0 of TMDR4, bits IOB3 to IOB0 of TIOR4, and bits CCR1 and CCR0 of TCR4, as well as the P25DDR bit. TPU Channel 4 Setting Table Below (1)

  • Page 269

    Selection Method and Pin Functions P24/TIOCA4 Switches as follows according to the combinations of the TPU channel 4 setting made using bits MD3 to MD0 of TMDR4, bits IOA3 to IOA0 of TIOR4, and bits CCR1 and CCR0 of TCR4, as well as the P24DDR bit. TPU Channel 4 Setting Table Below (1)

  • Page 270

    Selection Method and Pin Functions P23/TIOCD3 Switches as follows according to the combinations of the TPU channel 3 setting made using bits MD3 to MD0 of TMDR3, bits IOD3 to IOD0 of TIOR3L, and bits CCLR2 to CCLR0 of TCR3, as well as the P23DDR bit. TPU Channel 3 Setting Table Below (1)

  • Page 271

    Selection Method and Pin Functions P22/TIOCC3 Switches as follows according to the combinations of the TPU channel 3 setting made using bits MD3 to MD0 of TMDR3, bits IOC3 to IOC0 of TIOR3L, and bits CCR2 to CCR0 of TCR3, as well as the P22DDR bit. TPU Channel 3 Setting Table Below (1)

  • Page 272

    Selection Method and Pin Functions P21/TIOCB3 Switches as follows according to the combinations of the TPU channel 3 setting made using bits MD3 to MD0 of TMDR3, bits IOB3 to IOB0 of TIOR3L, and bits CCR2 to CCR0 of TCR3, as well as the P21DDR bit. TPU Channel 3 Setting Table Below (1)

  • Page 273

    Selection Method and Pin Functions P20/TIOCA3 Switches as follows according to the combinations of the TPU channel 3 setting made using bits MD3 to MD0 of TMDR3, bits IOA3 to IOA0 of TIOR3L, and bits CCR2 to CCR0 of TCR3, as well as the P20DDR bit. TPU Channel 3 Setting Table Below (1)

  • Page 274

    Port 3 9.4.1 Overview Port 3 is an 8-bit I/O port. Port 3 is a multi-purpose port for SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1), and external interrupt input pins (IRQ4, IRQ5). All of the port 3 pin functions have the same operating mode.

  • Page 275

    Port 3 Data Direction Register (P3DDR) P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value Read/Write P3DDR is an 8-bit write-dedicated register, which specifies the I/O for each port 3 pin by bit. Read is disenabled. If a read is carried out, undefined values are read out. By setting P3DDR to 1, the corresponding port 3 pins become output, and be clearing to 0 they become input.

  • Page 276

    Port 3 Register (PORT3) Initial value —* —* —* —* —* —* —* —* Read/Write Note: * Determined by the state of pins P37 to P30. PORT3 is an 8-bit read-dedicated register, which reflects the state of pins. Write is disenabled. Always carry out writing off output data of port 3 pins (P37 to P30) to P3DR without fail.

  • Page 277

    9.4.3 Pin Functions The port 3 pins also function as SCI I/O input pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1) and as external interrupt input pins (IRQ4 and IRQ5). The functions of port 3 pins are shown in Table 9-7. Table 9-7 Port 3 Pin Functions Selection Method and Pin Functions...

  • Page 278

    Selection Method and Pin Functions P33/TxD1 Switches as follows according to combinations of bit TE of SCR1 and bit P33DDR. P33DDR — Pin function P33 input pin P33 output pin* TxD1 output pin* Note: * When P33ODR = 1, it becomes NMOS open drain output. P32/SCK0/ Switches as follows according to combinations of bit C/A of SMR0, bits CKE0 and IRQ4...

  • Page 279

    Port 4 9.5.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7). Port 4 pin functions are the same in all operating modes. Figure 9-4 shows the port 4 pin configuration.

  • Page 280

    9.5.2 Register Configuration Table 9-8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 9-8 Port 4 Registers Name Abbreviation Initial Value Address* Port 4 register PORT4 Undefined H'FFB3...

  • Page 281

    9-5 (1) and 9-5 (2) show the pin functions for port 5. Port 5 pins Port 5 (I/O) (I/O) (I/O) Figure 9-5 (1) Port 5 Pin Functions (H8S/2646, H8S/2646R, H8S/2645) Port 5 pins Port 5 (I/O) / SCK2 (I/O) (I/O) / RxD2 (input) (I/O) / TxD2 (output)

  • Page 282

    9.6.2 Register Configuration Table 9-9 shows the port 5 register configuration. Table 9-9 Port 5 Register Configuration Name Abbreviation Initial Value Address Port 5 data direction register P5DDR H'FE34 Port 5 data register P5DR H'FF04 Port 5 register PORT5 H'FFB4 Notes: *1 Lower 16 bits of the address.

  • Page 283

    H8S/2647, port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2). Table 9-10 (1) Port 5 Pin Functions (H8S/2646, H8S/2646R, H8S/2645) Selection Method and Pin Functions Switches as follows according to the setting of the P52DDR bit.

  • Page 284

    Table 9-10 (2) Port 5 Pin Functions (H8S/2648, H8S/2648R, H8S/2647) Selection Method and Pin Functions P52/SCK2 Switches as follows according to a combination of the C/A bit in SMR and bits CKE0 and CKE1 in SCR of SCI2, and the P52DDR bit. CKE1 —...

  • Page 285

    Port 9 9.7.1 Overview Port 9 is an 8-bit input-only port. Port 9 pins also function as A/D converter analog input pins (AN8 to AN11). Port 9 pin functions are the same in all operating modes. Figure 9-6 shows the port 9 pin configuration.

  • Page 286

    9.7.2 Register Configuration Table 9-11 shows the port 9 register configuration. Port 9 is an input-only port, and does not have a data direction register or data register. Table 9-11 Port 9 Registers Name Abbreviation Initial Value Address* Port 9 register PORT9 Undefined H'FFB8...

  • Page 287: Overview

    Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and LCD driver output pins (H8S/2646, H8S/2646R, H8S/2645: SEG24 to SEG21 and COM4 to COM1, H8S/2648, H8S/2648R, H8S/2647: SEG40 to Seg37 and COM4 to COM1). The pin functions change according to the operating mode.

  • Page 288

    9.8.2 Register Configuration Table 9-12 shows the port A register configuration. Table 9-12 Port A Registers Name Abbreviation Initial Value Address* Port A data direction register PADDR H'00 H'FE39 Port A data register PADR H'00 H'FF09 Port A register PORTA Undefined H'FFB9 Port A MOS pull-up control register...

  • Page 289

    Port A Data Register (PADR) PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial value : PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to PA0). PADR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

  • Page 290

    Port A MOS Pull-Up Control Register (PAPCR) PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in LPCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin.

  • Page 291

    Table 9-13 PA7 to PA4 Pin Functions Selection Method and Pin Functions H8S/2646 PA7/A23 Switches as follows according to the combinations of bits SGS3 to SGS0 of LCD H8S/2646R /SEG24 to driver LPCR, bits AE3 to AE0 of PFGR, and bits PA7DDR to PA4DDR of PADDR.

  • Page 292: Mos Input Pull-up Function

    9.8.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings in PFCR, in LPCR, and in DDR, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin.

  • Page 293

    9.9.1 Overview Port B is an 8-bit I/O port. Port B also functions as LCD driver output pins (H8S/2646, H8S/2646R, H8S/2645: SEG16 to SEG9, H8S/2648, H8S/2648R, H8S/2647: SEG32 to SEG9) and as address bus outputs. The pin functions are determined by the operating mode.

  • Page 294

    9.9.2 Register Configuration Table 9-16 shows the port B register configuration. Table 9-16 Port B Registers Name Abbreviation Initial Value Address* Port B data direction register PBDDR H'00 H'FE3A Port B data register PBDR H'00 H'FF0A Port B register PORTB Undefined H'FFBA Port B MOS pull-up control register...

  • Page 295

    Port B Register (PORTB) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PB7 to PB0. PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB7 to PB0) must always be performed on PBDR.

  • Page 296

    9.9.3 Pin Functions Port B pins also function as LCD driver output pins (H8S/2646, H8S/2646R, H8S/2645: SEG16 to SEG9, H8S/2648, H8S/2648R, H8S/2647: SEG32 to SEG25) and address bus outputs. The pin functions differ between modes 4 to 6 and mode 7. Port B pin functions are shown in table 9-17.

  • Page 297

    9.9.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. MOS input pull-up can be specified as on or off on an individual bit basis. In modes 4 to 6, if a pin is in the input state in accordance with the settings of PFCR, the LCD driver LPCR, and DDR, setting PBPCR to 1 turns on MOS input pull-up.

  • Page 298

    9.10.1 Overview Port C is an 8-bit I/O port. Port C also functions as LCD driver output pins (H8S/2646, H8S/2646R, H8S/2645: SEG8 to SEG1, H8S/2648, H8S/2648R, H8S/2647: SEG24 to SEG17) and as address bus outputs. The pin functions are determined by the operating mode.

  • Page 299

    9.10.2 Register Configuration Table 9-19 shows the port C register configuration. Table 9-19 Port C Registers Name Abbreviation Initial Value Address* Port C data direction register PCDDR H'00 H'FE3B Port C data register PCDR H'00 H'FF0B Port C register PORTC Undefined H'FFBB Port C MOS pull-up control register...

  • Page 300

    Port C Register (PORTC) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PC7 to PC0. PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC7 to PC0) must always be performed on PCDR.

  • Page 301

    9.10.3 Pin Functions Port C can function as LCD segment output pins (H8S/2646, H8S/2646R, H8S/2645: SEG8 to SEG1, H8S/2648, H8S/2648R, H8S/2647: SEG24 to SEG17) and as address bus outputs. The pin functions differ in modes 4, 5, 6, and 7. The port C pin functions are listed in table 9-20.

  • Page 302

    9.10.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis.

  • Page 303

    9.11 Port D 9.11.1 Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. In the H8S/2648, H8S/2648R, H8S/2647, port D pins also function as LCD driver output pins (SEG16 to SEG9). Port D has a built-in MOS input pull-up function that can be controlled by software.

  • Page 304

    9.11.2 Register Configuration Table 9-22 shows the port D register configuration. Table 9-22 Port D Registers Name Abbreviation Initial Value Address* Port D data direction register PDDDR H'00 H'FE3C Port D data register PDDR H'00 H'FF0C Port D register PORTD Undefined H'FFBC Port D MOS pull-up control register...

  • Page 305

    Port D Register (PORTD) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PD7 to PD0. PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD0) must always be performed on PDDR.

  • Page 306

    The function of pins on port D are as listed in tables 9-23 (1) and 9-23 (2). Table 9-23 (1) Port D Pin Functions (H8S/2646, H8S/2646R, H8S/2645) Pins Method of Selection and Pin Function...

  • Page 307

    9.11.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis.

  • Page 308

    9.12 Port E 9.12.1 Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. In the H8S/2648, H8S/2648R, and H8S/2647, port E pins also function as LCD driver output pins (SEG8 to SEG1).

  • Page 309

    9.12.2 Register Configuration Table 9-25 shows the port E register configuration. Table 9-25 Port E Registers Address * Name Abbreviation Initial Value Port E data direction register PEDDR H'00 H'FE3D Port E data register PEDR H'00 H'FF0D Port E register PORTE Undefined H'FFBD...

  • Page 310

    Port E Register (PORTE) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by state of pins PE7 to PE0. PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR.

  • Page 311

    9.12.3 Pin Functions The port E pin functions are listed in tables 9-26 (1) and 9-26 (2). Table 9-26 (1) Port E Pin Functions (H8S/2646, H8S/2646R, H8S/2645) Operating mode Modes 4 to 6 Mode 7 Bus width setting 16-bit mode 8-bit mode —...

  • Page 312

    Table 9-27 MOS Input Pull-Up States (Port E) Hardware Software In Other Modes Reset Standby Mode Standby Mode Operations ON/OFF ON/OFF 4 to 6 8-bit bus 16-bit bus Legend: OFF: MOS input pull-up is always off. ON/OFF: On when PEDDR = 0, PEPCR = 1, and the pin is not used as a segment driver; otherwise off.

  • Page 313

    9.13 Port F 9.13.1 Overview Port F is a 7-bit I/O port. Port F also functions as LCD driver output pins (SEG20 to SEG17), external interrupt input pins (IRQ2, IRQ3), the A/D trigger input pin (ADTRG), bus control signal I/O pins (AS, RD, HWR, LWR, WAIT), and as the system clock output pin (φ). Figure 9-12 shows the port F pin configuration.

  • Page 314

    9.13.2 Register Configuration Table 9-28 shows the port F register configuration. Table 9-28 Port F Registers Name Abbreviation R/W Initial Value Address Port F data direction register PFDDR H'80/H'00 H'FE3E Port F data register PFDR H'00 H'FF0E Port F register PORTF Undefined H'FFBE...

  • Page 315

    Port F Data Register (PFDR) — PF6DR PF5DR PF4DR PF3DR PF2DR — PF0DR Initial value : undefined — PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF6 to PF2, PF0). PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.

  • Page 316

    Switches as follows according to bit PF7DDR. PF7DDR Pin function PF7 input ø output PF6/AS/SEG20 Switches as follows according to the operating mode and the setting of SGS3 (H8S/2646, to SGS0 and bit PF6DDR. H8S/2646R, H8S/2645) PF6/AS/SEG36 (H8S/2648, Operating Mode...

  • Page 317

    H8S/2648, SEG35 SEG35 H8S/2648R, output output H8S/2647 PF4/HWR/SEG1 Switches as follows according to the operating mode and the setting of SGS3 8 (H8S/2646, to SGS0 and bit PF4DDR. H8S/2646R, H8S/2645) PF4/HWR/SEG34 (H8S/2648, Operating Mode Modes 4 to 6 Mode 7...

  • Page 318

    *2 When used as an external interrupt input pin, do not use it as an I/O pin for other functions. PF2/WAIT/SEG1 Switches as follows according to the operating mode, and the setting of bits 7 (H8S/2646, SGS3 to SGS0, the WAITE bit, and bit PF2DDR. H8S/2646R, H8S/2645)

  • Page 319

    9.14 Port H 9.14.1 Overview Port H is an 8-bit I/O port. Port H pins also function as motor control PWM timer output pins (PWM1A to PWM1H). Figure 9-13 shows the port H pin configuration. Port H pin PH7 (I/O) / PWM1H (output) PH6 (I/O) / PWM1G (output) PH5 (I/O) / PWM1F (output) PH4 (I/O) / PWM1E (output)

  • Page 320

    Port H Data Direction Register (PHDDR) PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR Initial value : PHDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port H. PHDDR cannot be read. If it is, an undefined value will be read. PHDDR is initialized to H'00 by a reset and in hardware standby mode.

  • Page 321

    9.14.3 Pin Functions As shown in Table 9-31, the port H pin functions can be switched, bit by bit, by changing the values of OE1A to OE1H of motor control PWM timer PWOCR1 and PHDDR. Table 9-31 Port H Pin Functions OE1A to OE1H PHDDR —...

  • Page 322

    9.15.2 Register Configuration Table 9-32 shows the port J register configuration. Table 9-32 Port J Registers Name Abbreviation Initial Value Address* Port J data direction register PJDDR H'00 H'FC21 Port J data register PJDR H'00 H'FC25 Port J register PORTJ Undefined H'FC29 Note: * Lower 16 bits of the address...

  • Page 323

    Port J Register (PORTJ) Initial value : —* —* —* —* —* —* —* —* Note: * Determined by the state of PJ7 to PJ0. PORTJ is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port J pins (PJ7 to PJ0) must always be performed on PJDR.

  • Page 324

    9.16 Port K 9.16.1 Overview Port K is a 2-bit I/O port. Figure 9-15 shows the pin functions for port K. Port K pins PK7 (I/O) PK6 (I/O) Port K Figure 9-15 Port K Pin Functions 9.16.2 Register Configuration Table 9-34 shows the port A register configuration. Table 9-34 Port K Registers Name Abbreviation...

  • Page 325

    Port K Data Direction Register (PKDDR) PK7DDR PK6DDR — — — — — — Initial value : Undefined Undefined Undefined Undefined Undefined Undefined — — — — — — PKDDR is an 8-bit write-only register that specifies whether individual bits are input or output for each of the pins in port K.

  • Page 326

    PKDDR and PKDR are initialized if a reset occurs and in the hardware standby mode, so the content of PORTK is determined by the pin states. The previous states are retained in the software standby mode. 9.16.3 Pin Functions The function of the port K pins changes with the operating mode, in accordance with the value of PKDDR, as shown in table 9-35.

  • Page 327: Section 10 16-bit Timer Pulse Unit (tpu)

    Section 10 16-Bit Timer Pulse Unit (TPU) 10.1 Overview The H8S/2646 Series has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 10.1.1 Features • Maximum 16-pulse input/output  A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3,...

  • Page 328

    • Fast access via internal 16-bit bus  Fast access is possible via a 16-bit bus interface • 26 interrupt sources  For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ...

  • Page 329

    Table 10-1 TPU Functions Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Count clock ø/1 ø/1 ø/1 ø/1 ø/1 ø/1 ø/4 ø/4 ø/4 ø/4 ø/4 ø/4 ø/16 ø/16 ø/16 ø/16 ø/16 ø/16 ø/64 ø/64 ø/64 ø/64 ø/64 ø/64...

  • Page 330

    Item Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 activation compare compare compare compare compare compare match or match or match or match or match or match or input capture input capture input capture input capture input capture input capture TGR0A...

  • Page 331

    10.1.2 Block Diagram Figure 10-1 shows a block diagram of the TPU. Interrupt request signals Channel 3: TGI3A Input/output pins TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4 TGI4B TIOCB4 TCI4V Channel 5: TIOCA5 TCI4U TIOCB5...

  • Page 332

    10.1.3 Pin Configuration Table 10-2 summarizes the TPU pins. Table 10-2 TPU Pins Channel Name Symbol Function Clock input A TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A phase input) Clock input B TCLKB Input External clock B input pin...

  • Page 333

    Channel Name Symbol Function Input capture/out TIOCA3 TGR3A input capture input/output compare compare match A3 output/PWM output pin Input capture/out TIOCB3 TGR3B input capture input/output compare compare match B3 output/PWM output pin Input capture/out TIOCC3 TGR3C input capture input/output compare compare match C3 output/PWM output pin Input capture/out...

  • Page 334

    10.1.4 Register Configuration Table 10-3 summarizes the TPU registers. Table 10-3 TPU Registers Channel Name Abbreviation Initial Value Address Timer control register 0 TCR0 H'00 H'FF10 Timer mode register 0 TMDR0 H'C0 H'FF11 Timer I/O control register 0H TIOR0H H'00 H'FF12 Timer I/O control register 0L TIOR0L...

  • Page 335

    Channel Name Abbreviation Initial Value Address Timer control register 3 TCR3 H'00 H'FE80 Timer mode register 3 TMDR3 H'C0 H'FE81 Timer I/O control register 3H TIOR3H H'00 H'FE82 Timer I/O control register 3L TIOR3L H'00 H'FE83 Timer interrupt enable register 3 TIER3 H'40 H'FE84 Timer status register 3...

  • Page 336

    10.2 Register Descriptions 10.2.1 Timer Control Register (TCR) Channel 0: TCR0 Channel 3: TCR3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value : Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2...

  • Page 337

    Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter clearing source. Bit 7 Bit 6 Bit 5 Channel CCLR2 CCLR1 CCLR0 Description 0, 3 TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture...

  • Page 338

    Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. ø/4 both edges = ø/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.

  • Page 339

    Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 (Initial value) Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input...

  • Page 340

    Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description Internal clock: counts on ø/1 (Initial value) Internal clock: counts on ø/4 Internal clock: counts on ø/16 Internal clock: counts on ø/64 External clock: counts on TCLKA pin input Internal clock: counts on ø/1024 Internal clock: counts on ø/256 Internal clock: counts on ø/4096...

  • Page 341: Timer Mode Register (tmdr)

    10.2.2 Timer Mode Register (TMDR) Channel 0: TMDR0 Channel 3: TMDR3 — — Initial value : — — Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 — — — — Initial value : — — — —...

  • Page 342

    Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved.

  • Page 343: Timer I/o Control Register (tior)

    10.2.3 Timer I/O Control Register (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : Channel 0: TIOR0L Channel 3: TIOR3L IOD3 IOD2 IOD1...

  • Page 344

    Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Bit 7 Bit 6 Bit 5 Bit 4...

  • Page 345

    Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR0D is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...

  • Page 346

    Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR1B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...

  • Page 347

    Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR3B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...

  • Page 348

    Bit 7 Bit 6 Bit 5 Bit 4 Channel IOD3 IOD2 IOD1 IOD0 Description TGR3D is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...

  • Page 349

    Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description TGR4B is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...

  • Page 350

    Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Bit 3 Bit 2 Bit 1 Bit 0 Channel...

  • Page 351

    Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description TGR0C is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...

  • Page 352

    Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR1A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...

  • Page 353

    Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR3A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...

  • Page 354

    Bit 3 Bit 2 Bit 1 Bit 0 Channel IOC3 IOC2 IOC1 IOC0 Description TGR3C is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output register 1 output at compare match Toggle output at compare match Output disabled Initial output is 1...

  • Page 355

    Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description TGR4A is Output disabled (Initial value) output Initial output is 0 0 output at compare match compare output 1 output at compare match register Toggle output at compare match Output disabled Initial output is 1...

  • Page 356: Timer Interrupt Enable Register (tier)

    10.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Channel 3: TIER3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : — — Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 TTGE — TCIEU TCIEV —...

  • Page 357

    Bit 7—A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE Description A/D conversion start request generation disabled (Initial value) A/D conversion start request generation enabled Bit 6—Reserved: It is always read as 1 and cannot be modified. Bit 5—Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5.

  • Page 358

    Bit 2—TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGIEC Description...

  • Page 359: Timer Status Register (tsr)

    10.2.5 Timer Status Register (TSR) Channel 0: TSR0 Channel 3: TSR3 — — — TCFV TGFD TGFC TGFB TGFA Initial value : — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Can only be written with 0 for flag clearing. Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4...

  • Page 360

    Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD Description...

  • Page 361

    Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD Description...

  • Page 362

    Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB Description [Clearing conditions] (Initial value) • When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 •...

  • Page 363: Timer Counter (tcnt)

    10.2.6 Timer Counter (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note: * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel.

  • Page 364: Timer General Register (tgr)

    10.2.7 Timer General Register (TGR) Initial value : : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers.

  • Page 365: Timer Start Register (tstr)

    10.2.8 Timer Start Register (TSTR) — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : — — TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.

  • Page 366: Timer Synchro Register (tsyr)

    10.2.9 Timer Synchro Register (TSYR) — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value : — — TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.

  • Page 367

    10.2.10 Module Stop Control Register A (MSTPCRA) MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value : MSTPCRA is an 8-bit readable/writable register that performs module stop mode control. When the MSTPA5 bit in MSTPCRA is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode.

  • Page 368: Interface To Bus Master

    10.3 Interface to Bus Master 10.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10-2.

  • Page 369

    Examples of 8-bit register access operation are shown in figures 10-3, 10-4, and 10-5. Internal data bus Module Bus interface master data bus Figure 10-3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus Module master Bus interface data bus...

  • Page 370

    10.4 Operation 10.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting.

  • Page 371: Basic Functions

    10.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 10-6 shows an example of the count operation setting procedure.

  • Page 372

    • Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up- count operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1.

  • Page 373

    Figure 10-8 illustrates periodic counter operation. Counter cleared by TGR TCNT value compare match H'0000 Time CST bit Flag cleared by software or DTC activation Figure 10-8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match.

  • Page 374

    • Examples of waveform output operation Figure 10-10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change.

  • Page 375

    Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.

  • Page 376

    • Example of input capture operation Figure 10-13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.

  • Page 377: Synchronous Operation

    10.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation.

  • Page 378

    Example of Synchronous Operation: Figure 10-15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source.

  • Page 379: Buffer Operation

    10.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10-5 shows the register combinations used in buffer operation.

  • Page 380

    • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10-17. Input capture signal Timer general...

  • Page 381

    Examples of Buffer Operation • When TGR is an output compare register Figure 10-19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.

  • Page 382

    • When TGR is an input capture register Figure 10-20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.

  • Page 383: Cascaded Operation

    10.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.

  • Page 384

    Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.

  • Page 385: Pwm Modes

    10.4.6 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register.

  • Page 386

    Table 10-7 PWM Output Registers and Output Pins Output Pins Channel Registers PWM Mode 1 PWM Mode 2 TGR0A TIOCA0 TIOCA0 TGR0B TIOCB0 TGR0C TIOCC0 TIOCC0 TGR0D TIOCD0 TGR1A TIOCA1 TIOCA1 TGR1B TIOCB1 TGR2A TIOCA2 TIOCA2 TGR2B TIOCB2 TGR3A TIOCA3 TIOCA3 TGR3B TIOCB3...

  • Page 387

    Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode setting procedure. [1] Select the counter clock with bits TPSC2 to PWM mode TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR.

  • Page 388

    TCNT value Counter cleared by TGRA compare match TGRA TGRB H'0000 Time TIOCA Figure 10-25 Example of PWM Mode Operation (1) Figure 10-26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform.

  • Page 389

    Figure 10-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRB rewritten TGRA TGRB TGRB rewritten TGRB rewritten H'0000 Time 0% duty TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten...

  • Page 390: Phase Counting Mode

    10.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.

  • Page 391

    Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 10-29 shows an example of phase counting mode 1 operation, and table 10-9 summarizes the TCNT up/down-count conditions.

  • Page 392

    • Phase counting mode 2 Figure 10-30 shows an example of phase counting mode 2 operation, and table 10-10 summarizes the TCNT up/down-count conditions. TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCNT value Up-count Down-count...

  • Page 393

    • Phase counting mode 3 Figure 10-31 shows an example of phase counting mode 3 operation, and table 10-11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...

  • Page 394

    • Phase counting mode 4 Figure 10-32 shows an example of phase counting mode 4 operation, and table 10-12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count...

  • Page 395

    Phase Counting Mode Application Example: Figure 10-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.

  • Page 396

    Channel 1 TCLKA Edge TCNT1 detection circuit TCLKB TGR1A (speed period capture) TGR1B (position period capture) TCNT0 TGR0A (speed control period) – TGR0C – (position control period) TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 10-33 Phase Counting Mode Application Example...

  • Page 397

    10.5 Interrupts 10.5.1 Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1.

  • Page 398

    Table 10-13 TPU Interrupts Channel Interrupt Source Description DTC Activation Priority TGI0A TGR0A input capture/compare match Possible High TGI0B TGR0B input capture/compare match Possible TGI0C TGR0C input capture/compare match Possible TGI0D TGR0D input capture/compare match Possible TCI0V TCNT0 overflow Not possible TGI1A TGR1A input capture/compare match Possible TGI1B...

  • Page 399: Dtc Activation

    Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.

  • Page 400

    10.6 Operation Timing 10.6.1 Input/Output Timing TCNT Count Timing: Figure 10-34 shows TCNT count timing in internal clock operation, and figure 10-35 shows TCNT count timing in external clock operation. ø Falling edge Rising edge Internal clock TCNT input clock TCNT N–1 Figure 10-34 Count Timing in Internal Clock Operation...

  • Page 401

    Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin.

  • Page 402

    Timing for Counter Clearing by Compare Match/Input Capture: Figure 10-38 shows the timing when counter clearing by compare match occurrence is specified, and figure 10-39 shows the timing when counter clearing by input capture occurrence is specified. ø Compare match signal Counter clear signal H'0000...

  • Page 403

    Buffer Operation Timing: Figures 10-40 and 10-41 show the timing in buffer operation. ø TCNT Compare match signal TGRA, TGRB TGRC, TGRD Figure 10-40 Buffer Operation Timing (Compare Match) ø Input capture signal TCNT TGRA, TGRB TGRC, TGRD Figure 10-41 Buffer Operation Timing (Input Capture)

  • Page 404: Interrupt Signal Timing

    10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. ø TCNT input clock TCNT Compare match signal...

  • Page 405

    TGF Flag Setting Timing in Case of Input Capture: Figure 10-43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. ø Input capture signal TCNT TGF flag TGI interrupt Figure 10-43 TGI Interrupt Timing (Input Capture)

  • Page 406

    TCFV Flag/TCFU Flag Setting Timing: Figure 10-44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing.

  • Page 407

    Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC is activated, the flag is cleared automatically. Figure 10-46 shows the timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag clearing by the DTC.

  • Page 408

    10.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width.

  • Page 409

    Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10-49 shows the timing in this case. TCNT write cycle ø...

  • Page 410

    Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10-50 shows the timing in this case. TCNT write cycle ø...

  • Page 411

    Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10-51 shows the timing in this case.

  • Page 412

    Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10-52 shows the timing in this case. TGR write cycle ø...

  • Page 413

    Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10-53 shows the timing in this case. TGR read cycle ø...

  • Page 414

    Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10-54 shows the timing in this case. TGR write cycle ø...

  • Page 415

    Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10-55 shows the timing in this case. Buffer register write cycle ø...

  • Page 416

    Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.

  • Page 417

    Figure 10-57 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the H8S/2646 Series, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin.

  • Page 419: Section 11 Programmable Pulse Generator (ppg)

    11.1 Overview The H8S/2646 Series has a built-in programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 and group 2) that can operate both simultaneously and independently.

  • Page 420

    11.1.2 Block Diagram Figure 11-1 shows a block diagram of the PPG. Compare match signals NDERH NDERL Control logic PO15 Pulse output PO14 PO13 pins, group 3 Internal PO12 PODRH NDRH PO11 data bus PO10 Pulse output pins, group 2 Pulse output pins, group 1 PODRL...

  • Page 421

    11.1.3 Pin Configuration Table 11-1 summarizes the PPG pins. Table 11-1 PPG Pins Name Symbol Function Pulse output 8 Output Group 2 pulse output Pulse output 9 Output Pulse output 10 PO10 Output Pulse output 11 PO11 Output Pulse output 12 PO12 Output Group 3 pulse output...

  • Page 422: Registers

    PCR setting, the NDRL address is H'FE2D. When the output triggers are different, the NDRL address is H'FE2F for group 0 and H'FE2D for group 1. *4 The H8S/2646 Series has no pins corresponding to pulse output groups 0 and 1.

  • Page 423

    11.2 Register Descriptions 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL) NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : NDERL NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial value : NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis.

  • Page 424: Output Data Registers H And L (podrh, Podrl)

    Note: * A bit that has been set for pulse output by NDER is read-only. PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output. However, the H8S/2646 Series has no pins corresponding to PODRL.

  • Page 425: Next Data Registers H And L (ndrh, Ndrl)

    H'FE2D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FE2F consists entirely of reserved bits that cannot be modified and are always read as 1. However, the H8S/2646 Series has no output pins corresponding to pulse output groups 0 and 1.

  • Page 426

    H'FE2F. Bits 3 to 0 of address H'FE2D and bits 7 to 4 of address H'FE2F are reserved bits that cannot be modified and are always read as 1. However, the H8S/2646 Series has no output pins corresponding to pulse output groups 0 and 1.

  • Page 427: Ppg Output Control Register (pcr)

    Address H'FE2D NDR7 NDR6 NDR5 NDR4 — — — — Initial value : — — — — Address H'FE2F — — — — NDR3 NDR2 NDR1 NDR0 Initial value : — — — — 11.2.5 PPG Output Control Register (PCR) G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a...

  • Page 428

    Bits 3 and 2—Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match that triggers pulse output group 1 (pins PO7 to PO4). However, the H8S/2646 Series has no output pins corresponding to pulse output group 1. Description...

  • Page 429: Ppg Output Mode Register (pmr)

    11.2.6 PPG Output Mode Register (PMR) G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value : PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB and the non-overlap margin is set in TGRA.

  • Page 430

    Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). However, the H8S/2646 Series has no pins corresponding to pulse output group 1. Bit 5 G1INV Description Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL)

  • Page 431

    Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4). However, the H8S/2646 Series has no pins corresponding to pulse output group 1. Bit 1 G1NOV Description Normal operation in pulse output group 1 (output values updated at compare match A...

  • Page 432: Port 1 Data Direction Register (p1ddr)

    11.2.7 Port 1 Data Direction Register (P1DDR) P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1.

  • Page 433

    11.3 Operation 11.3.1 Overview PPG pulse output is enabled when the corresponding bits in P1DDR and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values.

  • Page 434: Output Timing

    11.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. ø...

  • Page 435: Normal Pulse Output

    11.3.3 Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 11-4 shows a sample procedure for setting up normal pulse output. [1] Set TIOR to make TGRA an output Normal PPG output compare register (with output disabled) Select TGR functions [2] Set the PPG output trigger period Set TGRA value [3] Select the counter clock source...

  • Page 436

    Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which pulse output is used for cyclic five-phase pulse output. Compare match TCNT value TCNT TGRA H'0000 Time NDRH PODRH PO15 PO14 PO13 PO12 PO11 Figure 11-5 Normal Pulse Output Example (Five-Phase Pulse Output) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output...

  • Page 437: Non-overlapping Pulse Output

    11.3.4 Non-Overlapping Pulse Output Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11-6 shows a sample procedure for setting up non-overlapping pulse output. [1] Set TIOR to make TGRA and Non-overlapping PPG output TGRB an output compare registers (with output disabled) Select TGR functions [2] Set the pulse output trigger period in TGRB and the non-overlap...

  • Page 438

    Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary Non- Overlapping Output): Figure 11-7 shows an example in which pulse output is used for four- phase complementary non-overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 Time NDRH PODRH Non-overlap margin PO15 PO14 PO13...

  • Page 439

    [1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt.

  • Page 440: Inverted Pulse Output

    11.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11-7.

  • Page 441: Pulse Output Triggered By Input Capture

    11.3.6 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal.

  • Page 442

    11.4 Usage Notes Operation of Pulse Output Pins: Pins PO8 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins.

  • Page 443

    Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC.

  • Page 445: Section 12 Watchdog Timer

    The H8S/2646 Series has an on-chip watchdog timer with two channels (WDT0, WDT1). The WDT can also generate an internal reset signal for the H8S/2646 Series if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow.

  • Page 446

    12.1.2 Block Diagram Figures 12-1 (a) and 12-1 (b) show a block diagram of the WDT. Overflow ø/2 Interrupt ø/64 WOVI0 control ø/128 (interrupt request ø/512 signal) Clock Clock select ø/2048 ø/8192 ø/32768 Reset ø/131072 Internal reset signal * control Internal clock sources RSTCSR...

  • Page 447

    ø/2 øSUB/2 ø/64 WOVI1 øSUB/4 ø/128 Interrupt (Interrupt request signal) øSUB/8 ø/512 control Clock Overflow øSUB/16 Clock Internal NMI select ø/2048 øSUB/32 Interrupt request signal ø/8192 Reset øSUB/64 ø/32768 control øSUB/128 ø/131072 Internal reset signal* øSUB/256 Internal clock TCNT TCSR interface Module bus Legend:...

  • Page 448

    12.1.3 Pin Configuration There are no pins related to the WDT. 12.1.4 Register Configuration The WDT has five registers, as summarized in table 12-1. These registers control clock selection, WDT mode switching, and the reset signal. Table 12-1 WDT Registers Address Channel Name Abbreviation R/W...

  • Page 449

    12.2 Register Descriptions 12.2.1 Timer Counter (TCNT) Initial value : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), an internal reset, a NMI interrupt (only WDT1), or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR.

  • Page 450

    TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCSR0 (TCSR1) is initialized to H'18 (H'00) by a reset and in hardware standby mode. It is not initialized in software standby mode.

  • Page 451

    WDT0 Mode Select TCSR0 WT/IT Description Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows. (Initial value) Watchdog timer mode: A reset is issued when the TCNT overflows if the RSTE bit of RSTCSR is set to 1.* Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).

  • Page 452

    WDT0 TCSR Bit 3—Reserved Bit: It is always read as 1 and cannot be modified. WDT1 TCSR Bit 3—Reset or NMI (RST/NMI): This bit is used to choose between an internal reset request and an NMI request when the TCNT overflows during the watchdog timer mode. Bit 3 RTS/NMI Description...

  • Page 453

    WDT1 Input Clock Select Description Bit 4 Bit 2 Bit 1 Bit 0 Overflow Period* (where ø = 20 MHz) CKS2 CKS1 CKS0 Clock (where ø SUB = 32.768 kHz) ø/2 (initial value) 25.6 µs ø/64 819.2 µs ø/128 1.6 ms ø/512 6.6 ms ø/2048...

  • Page 454: Reset Control/status Register (rstcsr)

    (Initial value) Reset signal is generated if TCNT overflows Note: * The modules within the H8S/2646 Series are not reset, but TCNT and TCSR within the WDT are reset. Bit 5—Reserved: Always read as 0. Can only be written with 0.

  • Page 455: Notes On Register Access

    12.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions.

  • Page 456

    Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address H'FF76. It cannot be written to with byte instructions. Figure 12-3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE bits.

  • Page 457

    12.3 Operation 12.3.1 Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before overflow occurs.

  • Page 458

    TCNT value Overflow H'FF Time H'00 WT/IT= 1 WOVF= 1* Write H'00' WT/IT= 1 Write H'00' TME= 1 to TCNT TME= 1 to TCNT internal reset is generated Internal reset signal 515/516 states Legend : Timer mode select bit WT/IT : Timer enable bit Note: * The WOVF bit is set to 1 and then cleared to 0 by an internal reset.

  • Page 459: Interval Timer Operation

    12.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 12-5.

  • Page 460: Timing Of Setting Of Watchdog Timer Overflow Flag (wovf)

    In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2646 Series chip. Figure 12-7 shows the timing in this case. ø...

  • Page 461

    12.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be cleared to 0 in the interrupt handling routine. If an NMI request has been chosen in the watchdog timer mode, an NMI request is generated when a TCNT overflow occurs.

  • Page 462: Changing Value Of Pss And Cks2 To Cks0

    Internal Reset in Watchdog Timer Mode In watchdog timer mode, the H8S/2646 Series will not be reset internally if TCNT overflows while the RSTE bit is cleared to 0. When this module is used as a watchdog timer, the RSTE bit must be set to 1 beforehand.

  • Page 463: Section 13 Serial Communication Interface (sci)

    Section 13 Serial Communication Interface (SCI) 13.1 Overview The H8S/2646 Series is equipped with 2 or 3 independent serial communication interface (SCI) channels*. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function).

  • Page 464

     Receive error detection : Overrun errors detected • Full-duplex communication capability  The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously  Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data •...

  • Page 465

    13.1.2 Block Diagram Figure 13-1 shows a block diagram of the SCI. Internal Module data bus data bus SCMR ø ø/4 Baud rate generator ø/16 Transmission/ ø/64 reception control Parity generation Clock Parity check External clock Legend : Receive shift register : Receive data register : Transmit shift register : Transmit data register...

  • Page 466

    13.1.3 Pin Configuration Table 13-1 shows the serial pins for each SCI channel. Table 13-1 SCI Pins Channel Pin Name Symbol Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output...

  • Page 467

    13.1.4 Register Configuration The SCI has the internal registers shown in table 13-2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. Table 13-2 SCI Registers Channel Name Abbreviation...

  • Page 468

    13.2 Register Descriptions 13.2.1 Receive Shift Register (RSR) — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data.

  • Page 469: Transmit Shift Register (tsr)

    13.2.3 Transmit Shift Register (TSR) — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically.

  • Page 470: Serial Mode Register (smr)

    13.2.5 Serial Mode Register (SMR) STOP CKS1 CKS0 Initial value SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode.

  • Page 471

    Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting.

  • Page 472

    Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP Description...

  • Page 473: Serial Control Register (scr)

    Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from ø, ø/4, ø/16, and ø/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 13.2.8, Bit Rate Register (BRR).

  • Page 474

    Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request...

  • Page 475

    Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE Description...

  • Page 476

    Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin.

  • Page 477: Serial Status Register (ssr)

    13.2.7 Serial Status Register (SSR) TDRE RDRF ORER TEND MPBT Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits.

  • Page 478

    Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF Description [Clearing conditions] (Initial value) • When 0 is written to RDRF after reading RDRF = 1 • When the DTC is activated by an RXI interrupt and reads data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is...

  • Page 479

    Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 Description [Clearing condition] (Initial value) When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Notes: *1 The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.

  • Page 480

    Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND Description [Clearing conditions] •...

  • Page 481: Bit Rate Register (brr)

    13.2.8 Bit Rate Register (BRR) Initial value BRR is an 8-bit register that sets the serial transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in standby mode.

  • Page 482

    ø = 6.144 MHz ø = 7.3728 MHz ø = 8 MHz ø = 9.8304 MHz Bit Rate Error Error Error Error (bit/s) 0.08 –0.07 2 0.03 –0.26 0.00 0.00 0.16 0.00 0.00 0.00 0.16 0.00 0.00 0.00 0.16 0.00 1200 0.00 0.00...

  • Page 483

    ø = 14.7456 MHz ø = 16 MHz ø = 17.2032 MHz ø = 18 MHz Bit Rate Error Error Error Error (bit/s) 0.70 0.03 0.48 –0.12 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 0.00 0.16 1200 0.00 0.16 0.00...

  • Page 484

    Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ø = 4 MHz ø = 8 MHz ø = 10 MHz ø = 16 MHz ø = 20 MHz Bit Rate (bit/s) — — — — — — —...

  • Page 485

    The BRR setting is found from the following formulas. Asynchronous mode: ø × 10 – 1 64 × 2 × B 2n–1 Clocked synchronous mode: ø × 10 – 1 8 × 2 × B 2n–1 Where B: Bit rate (bit/s) N: BRR setting for baud rate generator (0 ≤...

  • Page 486

    Table 13-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 13-6 and 13-7 show the maximum bit rates with external clock input. Table 13-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) ø (MHz) Maximum Bit Rate (bit/s) 125000 4.9152 153600...

  • Page 487

    Table 13-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) ø (MHz) External Input Clock (MHz) Maximum Bit Rate (bit/s) 1.0000 62500 4.9152 1.2288 76800 1.2500 78125 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 2.0000 125000 9.8304 2.4576 153600 2.5000 156250...

  • Page 488: Smart Card Mode Register (scmr)

    13.2.9 Smart Card Mode Register (SCMR) — — — — SDIR SINV — SMIF Initial value — — — — — SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication mode.

  • Page 489: Module Stop Control Register B (mstpcrb)

    Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not affect the