Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series
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Hitachi 16-Bit Single-Chip Microcomputer
ADE-602-207C
Rev. 4.0
9/20/02
Hitachi, Ltd.
H8S/2646 Series
H8S/2646
HD6432646
H8S/2645
HD6432645
H8S/2647
HD6432647
H8S/2648
HD6432648
H8S/2646R F-ZTAT™
HD64F2646R
H8S/2648R F-ZTAT™
HD64F2648R
Hardware Manual

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  Summary of Contents for Hitachi H8S/2646

  • Page 1 Hitachi 16-Bit Single-Chip Microcomputer H8S/2646 Series H8S/2646 HD6432646 H8S/2645 HD6432645 H8S/2647 HD6432647 H8S/2648 HD6432648 H8S/2646R F-ZTAT™ HD64F2646R H8S/2648R F-ZTAT™ HD64F2648R Hardware Manual ADE-602-207C Rev. 4.0 9/20/02 Hitachi, Ltd.
  • Page 2 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
  • Page 3 General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
  • Page 5 Note: * F-ZTAT™ is a trademark of Hitachi, Ltd. Target Users: This manual was written for users who will be using the H8S/2646 Series in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
  • Page 6 H8S/2646 Series manuals: Manual Title ADE No. H8S/2646 Series Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083 Users manuals for development tools: Manual Title ADE No. C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual ADE-702-247 Simulator Debugger (for Windows) Users Manual...
  • Page 7 List of Items Revised or Added for This Version Section Page Description 2.10.2 Caution to 76, 77 Newly added observe when using The BSET, BCLR, BNOT, BST and BIST instructions read data in a unit of byte, bit manipulation then, after bit manipulation, they write data in a unit of byte. Therefore, caution instructions must be exercised when executing any of these instructions for registers and ports that include write-only bits.
  • Page 8 Section Page Description 9.13.2 Register Part F Data Register (PFDR) Configuration — PF6DR PF5DR PF4DR PF3DR PF2DR — PF0DR Initial value : undefined — 2nd line changed as follows PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF6 to PF2, PF0).
  • Page 9 Section Page Description 15.3.2 Initialization 565 to Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing after Hardware setting must be made each time a CAN node begins communication. The baud rate and bit timing settings are made in the bit configuration register (BCR).
  • Page 10 Section Page Description 15.3.2 Initialization 565 to Example: With a 1 Mb/s baud rate and a 20 MHz input clock: after Hardware 20 MHz Reset 1 Mb/s = 2 × (0 + 1) × (3 + 4 + 3) Bit Rate and Bit Set Values Actual Values Timing Settings...
  • Page 11 Section Page Description Error warning interrupt (TEC ≥ 96) 15.3.7 Interrupt IRR3 Interface Error warning interrupt (REC ≥ 96) IRR4 Table 15-5 HCAN IRR7 Overload frame transmission interrupt Interrupt Sources 15.5 Usage Notes Newly added 9. HTxD pin output HTxD pin output in error passive state in error passive state If the HRxD pin becomes fixed at 1 during message transmission or 10.
  • Page 12 Section Page Description 23.1 Absolute Input voltage (OSC1, OSC2) –0.3 +3.5 Maximum Ratings lnput voltage (XTAL, EXTAL) –0.3 to A +0.3 Input voltage (ports 4 and 9) –0.3 to AV +0.3 Table 23-1 Input voltage (ports A, B, C, D, E, –0.3 to LPV +0.3 Absolute Maximum...
  • Page 13 Section Page Description B.2 Functions TXACK—Transmit Acknowledge Register H'F80A HCAN TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 — Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* — TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial value R/(W)* R/(W)* R/(W)* R/(W)*...
  • Page 14 Section Page Description B.2 Functions RFPR—Remote Request Register H'F810 HCAN RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 Initial value R/(W)* R/(W)* R/(W)* R/(W)*...
  • Page 15 Section Page Description B.2 Functions UMSR—Unread Message Status Register H'F81A HCAN UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 Initial value R/(W)* R/(W)* R/(W)*...
  • Page 17: Table Of Contents

    Contents Section 1 Overview..................1 Overview..........................Internal Block Diagram...................... Pin Description........................1.3.1 Pin Arrangement ....................1.3.2 Pin Functions in Each Operating Mode..............10 1.3.3 Pin Functions ......................20 Section 2 CPU....................27 Overview..........................27 2.1.1 Features ......................... 27 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU........28 2.1.3 Differences from H8/300 CPU ................
  • Page 18 Basic Timing........................71 2.9.1 Overview....................... 71 2.9.2 On-Chip Memory (ROM, RAM)................71 2.9.3 On-Chip Supporting Module Access Timing ............73 2.9.4 On-Chip HCAN Module Access Timing.............. 75 2.9.5 External Address Space Access Timing ............... 76 2.10 Usage Note ......................... 76 2.10.1 TAS Instruction ....................
  • Page 19 Section 5 Interrupt Controller ................101 Overview..........................101 5.1.1 Features ......................... 101 5.1.2 Block Diagram...................... 102 5.1.3 Pin Configuration....................103 5.1.4 Register Configuration..................103 Register Descriptions ......................104 5.2.1 System Control Register (SYSCR)............... 104 5.2.2 Interrupt Priority Registers A to H, J, K, M (IPRA to IPRH, IPRJ, IPRK, IPRM)..............
  • Page 20 6.2.3 Break Control Register A (BCRA) ............... 132 6.2.4 Break Control Register B (BCRB) ............... 134 6.2.5 Module Stop Control Register C (MSTPCRC) ............ 134 Operation..........................135 6.3.1 PC Break Interrupt Due to Instruction Fetch............135 6.3.2 PC Break Interrupt Due to Data Access ............... 135 6.3.3 Notes on PC Break Interrupt Handling..............
  • Page 21 Write Data Buffer Function ....................178 Bus Arbitration........................179 7.8.1 Overview ......................179 7.8.2 Operation ......................179 7.8.3 Bus Transfer Timing ..................... 179 Resets and the Bus Controller.................... 180 Section 8 Data Transfer Controller (DTC) ............181 Overview..........................181 8.1.1 Features ......................... 181 8.1.2 Block Diagram......................
  • Page 22 9.2.3 Pin Functions ......................224 Port 2..........................232 9.3.1 Overview....................... 232 9.3.2 Register Configuration..................232 9.3.3 Pin Functions ......................234 Port 3..........................242 9.4.1 Overview....................... 242 9.4.2 Register Configuration..................242 9.4.3 Pin Functions ......................245 Port 4..........................247 9.5.1 Overview....................... 247 9.5.2 Register Configuration..................
  • Page 23 9.12.2 Register Configuration..................277 9.12.3 Pin Functions ......................279 9.12.4 MOS Input Pull-Up Function................279 9.13 Port F..........................281 9.13.1 Overview....................... 281 9.13.2 Register Configuration..................282 9.13.3 Pin Functions ......................284 9.14 Port H ..........................287 9.14.1 Overview....................... 287 9.14.2 Register Configuration..................287 9.14.3 Pin Functions ......................
  • Page 24 10.4.3 Synchronous Operation ..................345 10.4.4 Buffer Operation ....................347 10.4.5 Cascaded Operation ....................351 10.4.6 PWM Modes ......................353 10.4.7 Phase Counting Mode ................... 358 10.5 Interrupts ..........................365 10.5.1 Interrupt Sources and Priorities ................365 10.5.2 DTC Activation ....................367 10.5.3 A/D Converter Activation..................
  • Page 25 12.1.4 Register Configuration..................416 12.2 Register Descriptions ......................417 12.2.1 Timer Counter (TCNT)..................417 12.2.2 Timer Control/Status Register (TCSR) ..............417 12.2.3 Reset Control/Status Register (RSTCSR) ............422 12.2.4 Notes on Register Access..................423 12.3 Operation..........................425 12.3.1 Watchdog Timer Operation .................. 425 12.3.2 Interval Timer Operation ..................
  • Page 26 14.3.6 Data Transfer Operations..................518 14.3.7 Operation in GSM Mode ..................525 14.3.8 Operation in Block Transfer Mode ............... 526 14.4 Usage Notes ........................527 Section 15 Hitachi Controller Area Network (HCAN) ........531 15.1 Overview..........................531 15.1.1 Features ......................... 531 15.1.2 Block Diagram...................... 532 15.1.3 Pin Configuration....................
  • Page 27 15.2.15 Transmit Error Counter (TEC)................554 15.2.16 Unread Message Status Register (UMSR)............555 15.2.17 Local Acceptance Filter Masks (LAFML, LAFMH) ........... 556 15.2.18 Message Control (MC0 to MC15)................ 557 15.2.19 Message Data (MD0 to MD15) ................561 15.2.20 Module Stop Control Register C (MSTPCRC) ............ 561 15.3 Operation..........................
  • Page 28 17.1.4 Register Configuration..................615 17.2 Register Descriptions ......................616 17.2.1 PWM Control Registers 1 and 2 (PWCR1, PWCR2)........... 616 17.2.2 PWM Output Control Registers 1 and 2 (PWOCR1, PWOCR2)......617 17.2.3 PWM Polarity Registers 1 and 2 (PWPR1, PWPR2) ........... 618 17.2.4 PWM Counters 1 and 2 (PWCNT1, PWCNT2) ...........
  • Page 29 19.3 Operation..........................655 19.4 Usage Notes ........................655 Section 20 ROM....................657 20.1 Features ..........................657 20.2 Overview..........................658 20.2.1 Block Diagram...................... 658 20.2.2 Mode Transitions ....................659 20.2.3 On-Board Programming Modes................660 20.2.4 Flash Memory Emulation in RAM ............... 662 20.2.5 Differences between Boot Mode and User Program Mode........
  • Page 30 20.11.8 Programmer Mode Transition Time ..............707 20.11.9 Notes on Memory Programming ................708 20.12 Flash Memory and Power-Down States ................709 20.12.1 Notes on Power-Down States ................709 20.13 Flash Memory Programming and Erasing Precautions............710 Section 21 Clock Pulse Generator ..............715 21.1 Overview..........................
  • Page 31 22.6.5 Usage Notes ......................744 22.7 Hardware Standby Mode ....................745 22.7.1 Hardware Standby Mode ..................745 22.7.2 Hardware Standby Mode Timing................746 22.8 Watch Mode ........................746 22.8.1 Watch Mode......................746 22.8.2 Exiting Watch Mode ..................... 747 22.8.3 Notes ........................747 22.9 Sub-Sleep Mode .........................
  • Page 32 Appendix C I/O Port Block Diagrams............1075 Port 1 Block Diagrams ...................... 1075 Port 2 Block Diagrams ......................1081 Port 3 Block Diagrams ...................... 1083 Port 4 Block Diagram ....................... 1090 Port 5 Block Diagrams ...................... 1091 Port 9 Block Diagram ....................... 1095 Port A Block Diagram.......................
  • Page 33: Section 1 Overview

    Section 1 Overview Overview The H8S/2646 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
  • Page 34 Table 1-1 Overview Item Specification • General-register machine  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control  Maximum clock rate: 20 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract : 50 ns 16 ×...
  • Page 35 Segment output pins may be selected four at a time as ports • On-chip power supply division resistor Notes: *1 In the H8S/2646, H8S/2646R, and H8S/2645. *2 In the H8S/2648, H8S/2648R, and H8S/2647. • 92 I/O pins, 16 input-only pins...
  • Page 36 2 kbytes H8S/2647 • Seven external interrupt pins (NMI, IRQ0 to IRQ5) Interrupt controller • Internal interrupt sources  43 (H8S/2646, H8S/2646R, H8S/2645)  47 (H8S/2648, H8S/2648R, H8S/2647) • Eight priority levels settable Power-down states • Medium-speed mode • Sleep mode •...
  • Page 37 Item Specification Product lineup Model Name Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Packages HD6432646 HD64F2646R 128 k/4 k FP-144J HD6432645 — 64 k/2 k FP-144G HD6432648 HD64F2648R 128 k/4 k FP-144J HD6432647 — 64 k/2 k FP-144G The HD64F2646R and HD64F2648R use an FP-144J package.
  • Page 38: Internal Block Diagram

    P93/AN11 P92/AN10 P91/AN9 Port 1 Port H Port J Port 4 P90/AN8 Notes: *1 Flash memory version only. *2 The FWE pin is for compatibility with the flash memory version. Figure 1-1 (1) H8S/2646, H8S/2646R, and H8S/2645 Internal Block Diagram...
  • Page 39 Port D Port E PA7/A23/SEG40 PA6/A22/SEG39 OSC2 PA5/A21/SEG38 OSC1 PA4/A20/SEG37 EXTAL PA3/A19/COM4 XTAL PA2/A18/COM3 PLLCAP PA1/A17/COM2 H8S/2600 CPU PLLVSS PA0/A16/COM1 STBY PB7/A15/SEG32 PB6/A14/SEG31 PB5/A13/SEG30 PB4/A12/SEG29 HTxD Interrupt controller PB3 / A11/SEG28 HRxD PB2/A10/SEG27 PB1/A9/SEG26 PC break controller PF7/ø PB0/A8/SEG25 PF6/AS/SEG36 PC7/A7/SEG24 PF5/RD/SEG35 PC6/A6/SEG23...
  • Page 40: Pin Description

    Pin Description 1.3.1 Pin Arrangement Figure 1-2 (1) shows the pin arrangement of the H8S/2646, H8S/2646R, and H8S/2645, and figure 1-2 (2) shows that of the H8S/2648, H8S/2648R, and H8S/2647. HTxD PWMVSS HRxD PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E P20/TIOCA3 PWMVCC P21/TIOCB3...
  • Page 41 HTxD PWMVSS HRxD PJ7/PWM2H P50/TxD2 PJ6/PWM2G P51/RxD2 PJ5/PWM2F P52/SCK2 PJ4/PWM2E P20/TIOCA3 PWMVCC P21/TIOCB3 PJ3/PWM2D P22/TIOCC3 PJ2/PWM2C P23/TIOCD3 PJ1/PWM2B P25/TIOCB4 PJ0/PWM2A PWMVSS P24/TIOCA4 PH7/PWM1H PH6/PWM1G P27/TIOCB5 PH5/PWM1F PH4/PWM1E P26/TIOCA5 PWMVCC PH3/PWM1D Top View AVCC PH2/PWM1C Vref (FP-144J, FP-144G) PH1/PWM1B P40/AN0 PH0/PWM1A P41/AN1 PWMVSS P42/AN2...
  • Page 42: Pin Functions In Each Operating Mode

    1.3.2 Pin Functions in Each Operating Mode Tablse 1-2 (1) and 1-2 (2) show the pin functions in each of the operating modes. Table 1-2 (1) Pin Functions in Each Operating Mode (H8S/2646, H8S/2646R, H8S/2645) Pin Name Pin No. Mode 4...
  • Page 43 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PC6/A6/SEG7 PC6/SEG7 PC7/A7/SEG8 PC7/SEG8 PB0/A8/SEG9 PB0/A8/SEG9 PB0/A8/SEG9 PB0/SEG9 PB1/A9/SEG10 PB1/A9/SEG10 PB1/A9/SEG10 PB1/SEG10 PB2/A10/SEG11 PB2/A10/SEG11 PB2/A10/SEG11 PB2/SEG11 PB3/A11/SEG12 PB3/A11/SEG12 PB3/A11/SEG12 PB3/SEG12 PB4/A12/SEG13 PB4/A12/SEG13 PB4/A12/SEG13 PB4/SEG13 PB5/A13/SEG14 PB5/A13/SEG14 PB5/A13/SEG14 PB5/SEG14 PB6/A14/SEG15 PB6/A14/SEG15 PB6/A14/SEG15...
  • Page 44 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PWMVss PWMVss PWMVss PWMVss PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PWMVcc PWMVcc PWMVcc PWMVcc PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ5/PWM2F PJ5/PWM2F PJ5/PWM2F...
  • Page 45 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 XTAL XTAL XTAL XTAL EXTAL EXTAL EXTAL EXTAL PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/ADTRG/IRQ3 PF7/φ PF7/φ PF7/φ PF7/φ P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/...
  • Page 46 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 AVcc AVcc AVcc AVcc Vref Vref Vref Vref P40/AN0 P40/AN0 P40/AN0 P40/AN0 P41/AN1 P41/AN1 P41/AN1 P41/AN1 P42/AN2 P42/AN2 P42/AN2 P42/AN2 P43/AN3 P43/AN3 P43/AN3...
  • Page 47 Table 1-2 (2) Pin Functions in Each Operating Mode (H8S/2648, H8S/2648R, H8S/2647) Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PE0/D0/SEG1 PE0/D0/SEG1 PE0/D0/SEG1 PE0/SEG1 PE1/D1/SEG2 PE1/D1/SEG2 PE1/D1/SEG2 PE1/SEG2 PE2/D2/SEG3 PE2/D2/SEG3 PE2/D2/SEG3 PE2/SEG3 PE3/D3/SEG4 PE3/D3/SEG4 PE3/D3/SEG4 PE3/SEG4 PE4/D4/SEG5 PE4/D4/SEG5 PE4/D4/SEG5...
  • Page 48 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PC6/A6/SEG23 PC6/SEG23 PC7/A7/SEG24 PC7/SEG24 PB0/A8/SEG25 PB0/A8/SEG25 PB0/A8/SEG25 PB0/SEG25 PB1/A9/SEG26 PB1/A9/SEG26 PB1/A9/SEG26 PB1/SEG26 PB2/A10/SEG27 PB2/A10/SEG27 PB2/A10/SEG27 PB2/SEG27 PB3/A11/SEG28 PB3/A11/SEG28 PB3/A11/SEG28 PB3/SEG28 PB4/A12/SEG29 PB4/A12/SEG29 PB4/A12/SEG29 PB4/SEG29 PB5/A13/SEG30 PB5/A13/SEG30 PB5/A13/SEG30 PB5/SEG30 PB6/A14/SEG31 PB6/A14/SEG31 PB6/A14/SEG31...
  • Page 49 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 PWMVss PWMVss PWMVss PWMVss PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ0/PWM2A PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ1/PWM2B PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ2/PWM2C PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PJ3/PWM2D PWMVcc PWMVcc PWMVcc PWMVcc PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ4/PWM2E PJ5/PWM2F PJ5/PWM2F PJ5/PWM2F...
  • Page 50 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 XTAL XTAL XTAL XTAL EXTAL EXTAL EXTAL EXTAL PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF0/IRQ2 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/LWR/ADTRG/IRQ3 PF3/ADTRG/IRQ3 PF7/φ PF7/φ PF7/φ PF7/φ P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P10/PO8/TIOCA0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P11/PO9/TIOCB0 P12/PO10/TIOCC0/ P12/PO10/TIOCC0/ P12/PO10/TIOCC0/...
  • Page 51 Pin Name Pin No. Mode 4 Mode 5 Mode 6 Mode 7 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P27/TIOCB5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 P26/TIOCA5 AVcc AVcc AVcc AVcc Vref Vref Vref Vref P40/AN0 P40/AN0 P40/AN0 P40/AN0 P41/AN1 P41/AN1 P41/AN1 P41/AN1 P42/AN2 P42/AN2 P42/AN2 P42/AN2 P43/AN3 P43/AN3 P43/AN3...
  • Page 52: Pin Functions

    1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2646. Table 1-3 Pin Functions Type Symbol Name and Function Power Input Power supply: For connection to the power supply. All Vcc pins should be connected to the system power supply.
  • Page 53 Mode pins: These pins set the operating mode. control The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2646 Series is operating. Operating Mode —...
  • Page 54 Type Symbol Name and Function Bus control Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled.
  • Page 55 Transmit data: Data output pins. communication interface (SCI)/ Smart Card RxD1, RxD0 Input Receive data: Data input pins. interface H8S/2646, SCK1, SCK0 I/O Serial clock: Clock I/O pins. H8S/2646R, The SCK0 output type is NMOS push-pull. H8S/2645 Serial TxD2 to Output Transmit data: Data output pins.
  • Page 56 Type Symbol Name and Function SEG24 to Output LCD segment output: LCD segment output pins controller/driver SEG1 (H8S/2646, H8S/2646R, H8S/2645) SEG40 to SEG1 (H8S/2648, H8S/2648R, H8S/2647) COM4 to Output LCD common output: LCD common output pins COM1 I/O ports P17 to P10 Port 1: 8-bit I/O pins.
  • Page 57 Type Symbol Name and Function I/O ports PF7 to PF2, Port F: 7-bit I/O pins. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). PH7 to PH0 Port H: 8-bit I/O pins. Input or output can be designated for each bit by means of the port H data direction register (PHDDR).
  • Page 59: Section 2 Cpu

    Section 2 CPU Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control.
  • Page 60: Differences Between H8S/2600 Cpu And H8S/2000 Cpu

     32 ÷ 16-bit register-register divide : 1000 ns • Two CPU operating modes  Normal mode*  Advanced mode Note: * Not available in the H8S/2646 Series. • Power-down state  Transition to power-down state by SLEEP instruction  CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
  • Page 61: Differences From H8/300 Cpu

     Normal mode* supports the same 64-kbyte address space as the H8/300 CPU.  Advanced mode supports a maximum 16-Mbyte address space. Note: * Not available in the H8S/2646 Series. • Enhanced addressing  The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
  • Page 62: Cpu Operating Modes

    Note: * Not available in the H8S/2646 Series. Figure 2-1 CPU Operating Modes (1) Normal Mode (Not Available in the H8S/2646 Series) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed.
  • Page 63 Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2-2).
  • Page 64 Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is not pushed onto the stack.
  • Page 65 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). For details of the exception vector table, see section 4, Exception Handling.
  • Page 66 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When EXR is invalid, it is not pushed onto the stack.
  • Page 67: Address Space

    (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2646 Series H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Note: * Not available in the H8S/2646 Series. Figure 2-6 Memory Map...
  • Page 68: Register Configuration

    Interrupt mask bits Overflow flag CCR: Condition-code register Carry flag Interrupt mask bit MAC: Multiply-accumulate register User bit or interrupt mask bit* Note: * Cannot be used as an interrupt mask bit in the H8S/2646 Series. Figure 2-7 CPU Registers...
  • Page 69: General Registers

    2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
  • Page 70: Control Registers

    General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. Free area SP (ER7) Stack area Figure 2-9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),...
  • Page 71 Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
  • Page 72: Initial Register Values

    Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, Instruction List. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
  • Page 73: Data Formats

    Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
  • Page 74 Data Type Register Number Data Format Word data Word data Longword data Legend ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-10 General Register Data Formats (cont)
  • Page 75: Memory Data Formats

    2.5.2 Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
  • Page 76: Instruction Set

    @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. *2 Bcc is the general name for conditional branch instructions. *3 Not available in the H8S/2646 Series. *4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
  • Page 77: Instructions And Addressing Modes

    2.6.2 Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes...
  • Page 79: Table Of Instructions Classified By Function

    2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs)
  • Page 80 Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in the H8S/2646 Series. MOVTPE Cannot be used in the H8S/2646 Series. @SP+ → Rn Pops a register from the stack.
  • Page 81 Type Instruction Size Function Rd ± Rs → Rd, Rd ± #IMM → Rd Arithmetic B/W/L operations Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register.
  • Page 82 Type Instruction Size Function Rd ÷ Rs → Rd Arithmetic DIVXS operations Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16- bit remainder.
  • Page 83 Type Instruction Size Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Logic B/W/L operations Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
  • Page 84 Type Instruction Size Function 1 → (<bit-No.> of <EAd>) Bit- BSET manipulation Sets a specified bit in a general register or memory instructions operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
  • Page 85 Type Instruction Size Function C ⊕ (<bit-No.> of <EAd>) → C Bit- BXOR manipulation Exclusive-ORs the carry flag with a specified bit in a instructions general register or memory operand and stores the result in the carry flag. C ⊕ [¬ (<bit-No.> of <EAd>) ] → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand...
  • Page 86 Type Instruction Size Function Branch — Branches to a specified address if a specified condition instructions is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨ Z = 0 High C ∨...
  • Page 87 Type Instruction Size Function System control TRAPA — Starts trap-instruction exception handling. instructions — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR.
  • Page 88: Basic Instruction Formats

    Type Instruction Size Function if R4L ≠ 0 then Block data EEPMOV.B — Repeat @ER5+ → @ER6+ transfer R4L–1 → R4L instruction Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next;...
  • Page 89 Figure 2-12 shows examples of instruction formats. (1) Operation field only NOP, RTS, etc. (2) Operation field and register fields ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field EA (disp) BRA d:16, etc...
  • Page 90: Addressing Modes And Effective Address Calculation

    Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
  • Page 91 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction 24 bits (@aa:24) address Note: * Not available in the H8S/2646 Series.
  • Page 92 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the H8S/2646 Series.
  • Page 93: Effective Address Calculation

    (a) Normal Mode * (b) Advanced Mode Note: * Not available in the H8S/2646 Series. Figure 2-13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address.
  • Page 94 Table 2-6 Effective Address Calculation...
  • Page 97: Processing States

    Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
  • Page 98: Reset State

    End of bus request Bus request Program execution state Bus-released state Sleep mode External interrupt request Software standby mode Exception handling state RES= High STBY= High, RES= Low Reset state Hardware standby mode Power-down state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: *1 goes low.
  • Page 99: Exception-Handling State

    2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions.
  • Page 100 (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the reset state when the RES is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address.
  • Page 101 (b) Interrupt control mode 2 Advanced mode Reserved (24 bits) (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Notes: *1 Ignored when returning. *2 Not available in the H8S/2646 Series. Figure 2-16 Stack Structure after Exception Handling (Examples)
  • Page 102: Program Execution State

    2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU is data transfer controller (DTC).
  • Page 103: Basic Timing

    Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states.
  • Page 104 Bus cycle ø Address bus Held High High HWR, LWR High Data bus High-impedance state Figure 2-18 Pin States during On-Chip Memory Access...
  • Page 105: On-Chip Supporting Module Access Timing

    2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access cycle for the on-chip supporting modules. Figure 2-20 shows the pin states. Bus cycle ø...
  • Page 106 Bus cycle ø Held Address bus High High HWR, LWR High Data bus High-impedance state Figure 2-20 Pin States during On-Chip Supporting Module Access...
  • Page 107: On-Chip Hcan Module Access Timing

    2.9.4 On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access cycle is shown in figures 2-21 and 2-22, and the pin states in figure 2-23.
  • Page 108: External Address Space Access Timing

    Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used.
  • Page 109 The BCLR instruction can be used to clear the flag of an internal I/O register to 0. In that case, if it is clearly known that the pertinent flag is set to 1 in an interrupt processing routine or other processing, there is no need to read the flag in advance.
  • Page 111: Section 3 Mcu Operating Modes

    3.1.1 Operating Mode Selection The H8S/2646 Series has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0).
  • Page 112: Register Configuration

    The H8S/2646 Series can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration...
  • Page 113: System Control Register (Syscr)

    3.2.2 System Control Register (SYSCR) MACS — INTM1 INTM0 NMIEG — — RAME Initial value — — SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI, and enables or disenables on-chip RAM.
  • Page 114: Pin Function Control Register (Pfcr)

    Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG Description An interrupt is requested at the falling edge of NMI input (Initial value) An interrupt is requested at the rising edge of NMI input Bit 2—...
  • Page 115 Bit 3 Bit 2 Bit 1 Bit 0 Description A8–A23 address output disabled (Initial value*) A8 address output enabled; A9–A23 address output disabled A8, A9 address output enabled; A10–A23 address output disabled A8–A10 address output enabled; A11–A23 address output disabled A8–A11 address output enabled;...
  • Page 116: Operating Mode Descriptions

    Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals.
  • Page 117: Pin Functions In Each Operating Mode

    *: After reset Address Map in Each Operating Mode A address maps of the H8S/2646 Series are shown in figures 3-1 (1) and 3-1 (2). The address space is 16 Mbytes in modes 4 to 7 (advanced modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus...