Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
General Precautions on the Handling of Products 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed.
Note: * F-ZTAT™ is a trademark of Hitachi, Ltd. Target Users: This manual was written for users who will be using the H8S/2646 Series in the design of application systems. Members of this audience are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers.
H8S/2646 Series manuals: Manual Title ADE No. H8S/2646 Series Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Programming Manual ADE-602-083 Users manuals for development tools: Manual Title ADE No. C/C++ Complier, Assembler, Optimized Linkage Editor User's Manual ADE-702-247 Simulator Debugger (for Windows) Users Manual...
List of Items Revised or Added for This Version Section Page Description 2.10.2 Caution to 76, 77 Newly added observe when using The BSET, BCLR, BNOT, BST and BIST instructions read data in a unit of byte, bit manipulation then, after bit manipulation, they write data in a unit of byte. Therefore, caution instructions must be exercised when executing any of these instructions for registers and ports that include write-only bits.
Section Page Description 9.13.2 Register Part F Data Register (PFDR) Configuration — PF6DR PF5DR PF4DR PF3DR PF2DR — PF0DR Initial value : undefined — 2nd line changed as follows PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF6 to PF2, PF0).
Section Page Description 15.3.2 Initialization 565 to Bit Rate and Bit Timing Settings: As bit rate settings, a baud rate setting and bit timing after Hardware setting must be made each time a CAN node begins communication. The baud rate and bit timing settings are made in the bit configuration register (BCR).
Section Page Description 15.3.2 Initialization 565 to Example: With a 1 Mb/s baud rate and a 20 MHz input clock: after Hardware 20 MHz Reset 1 Mb/s = 2 × (0 + 1) × (3 + 4 + 3) Bit Rate and Bit Set Values Actual Values Timing Settings...
Section Page Description Error warning interrupt (TEC ≥ 96) 15.3.7 Interrupt IRR3 Interface Error warning interrupt (REC ≥ 96) IRR4 Table 15-5 HCAN IRR7 Overload frame transmission interrupt Interrupt Sources 15.5 Usage Notes Newly added 9. HTxD pin output HTxD pin output in error passive state in error passive state If the HRxD pin becomes fixed at 1 during message transmission or 10.
Section Page Description 23.1 Absolute Input voltage (OSC1, OSC2) –0.3 +3.5 Maximum Ratings lnput voltage (XTAL, EXTAL) –0.3 to A +0.3 Input voltage (ports 4 and 9) –0.3 to AV +0.3 Table 23-1 Input voltage (ports A, B, C, D, E, –0.3 to LPV +0.3 Absolute Maximum...
Section 5 Interrupt Controller ................101 Overview..........................101 5.1.1 Features ......................... 101 5.1.2 Block Diagram...................... 102 5.1.3 Pin Configuration....................103 5.1.4 Register Configuration..................103 Register Descriptions ......................104 5.2.1 System Control Register (SYSCR)............... 104 5.2.2 Interrupt Priority Registers A to H, J, K, M (IPRA to IPRH, IPRJ, IPRK, IPRM)..............
6.2.3 Break Control Register A (BCRA) ............... 132 6.2.4 Break Control Register B (BCRB) ............... 134 6.2.5 Module Stop Control Register C (MSTPCRC) ............ 134 Operation..........................135 6.3.1 PC Break Interrupt Due to Instruction Fetch............135 6.3.2 PC Break Interrupt Due to Data Access ............... 135 6.3.3 Notes on PC Break Interrupt Handling..............
Write Data Buffer Function ....................178 Bus Arbitration........................179 7.8.1 Overview ......................179 7.8.2 Operation ......................179 7.8.3 Bus Transfer Timing ..................... 179 Resets and the Bus Controller.................... 180 Section 8 Data Transfer Controller (DTC) ............181 Overview..........................181 8.1.1 Features ......................... 181 8.1.2 Block Diagram......................
Appendix C I/O Port Block Diagrams............1075 Port 1 Block Diagrams ...................... 1075 Port 2 Block Diagrams ......................1081 Port 3 Block Diagrams ...................... 1083 Port 4 Block Diagram ....................... 1090 Port 5 Block Diagrams ...................... 1091 Port 9 Block Diagram ....................... 1095 Port A Block Diagram.......................
Section 1 Overview Overview The H8S/2646 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2600 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
Table 1-1 Overview Item Specification • General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations 8/16/32-bit register-register add/subtract : 50 ns 16 ×...
Segment output pins may be selected four at a time as ports • On-chip power supply division resistor Notes: *1 In the H8S/2646, H8S/2646R, and H8S/2645. *2 In the H8S/2648, H8S/2648R, and H8S/2647. • 92 I/O pins, 16 input-only pins...
Item Specification Product lineup Model Name Mask ROM Version F-ZTAT Version ROM/RAM (Bytes) Packages HD6432646 HD64F2646R 128 k/4 k FP-144J HD6432645 — 64 k/2 k FP-144G HD6432648 HD64F2648R 128 k/4 k FP-144J HD6432647 — 64 k/2 k FP-144G The HD64F2646R and HD64F2648R use an FP-144J package.
P93/AN11 P92/AN10 P91/AN9 Port 1 Port H Port J Port 4 P90/AN8 Notes: *1 Flash memory version only. *2 The FWE pin is for compatibility with the flash memory version. Figure 1-1 (1) H8S/2646, H8S/2646R, and H8S/2645 Internal Block Diagram...
Port D Port E PA7/A23/SEG40 PA6/A22/SEG39 OSC2 PA5/A21/SEG38 OSC1 PA4/A20/SEG37 EXTAL PA3/A19/COM4 XTAL PA2/A18/COM3 PLLCAP PA1/A17/COM2 H8S/2600 CPU PLLVSS PA0/A16/COM1 STBY PB7/A15/SEG32 PB6/A14/SEG31 PB5/A13/SEG30 PB4/A12/SEG29 HTxD Interrupt controller PB3 / A11/SEG28 HRxD PB2/A10/SEG27 PB1/A9/SEG26 PC break controller PF7/ø PB0/A8/SEG25 PF6/AS/SEG36 PC7/A7/SEG24 PF5/RD/SEG35 PC6/A6/SEG23...
Pin Description 1.3.1 Pin Arrangement Figure 1-2 (1) shows the pin arrangement of the H8S/2646, H8S/2646R, and H8S/2645, and figure 1-2 (2) shows that of the H8S/2648, H8S/2648R, and H8S/2647. HTxD PWMVSS HRxD PJ7/PWM2H PJ6/PWM2G PJ5/PWM2F PJ4/PWM2E P20/TIOCA3 PWMVCC P21/TIOCB3...
1.3.2 Pin Functions in Each Operating Mode Tablse 1-2 (1) and 1-2 (2) show the pin functions in each of the operating modes. Table 1-2 (1) Pin Functions in Each Operating Mode (H8S/2646, H8S/2646R, H8S/2645) Pin Name Pin No. Mode 4...
1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2646. Table 1-3 Pin Functions Type Symbol Name and Function Power Input Power supply: For connection to the power supply. All Vcc pins should be connected to the system power supply.
Mode pins: These pins set the operating mode. control The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2646 Series is operating. Operating Mode —...
Type Symbol Name and Function Bus control Output High write: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled.
Transmit data: Data output pins. communication interface (SCI)/ Smart Card RxD1, RxD0 Input Receive data: Data input pins. interface H8S/2646, SCK1, SCK0 I/O Serial clock: Clock I/O pins. H8S/2646R, The SCK0 output type is NMOS push-pull. H8S/2645 Serial TxD2 to Output Transmit data: Data output pins.
Type Symbol Name and Function SEG24 to Output LCD segment output: LCD segment output pins controller/driver SEG1 (H8S/2646, H8S/2646R, H8S/2645) SEG40 to SEG1 (H8S/2648, H8S/2648R, H8S/2647) COM4 to Output LCD common output: LCD common output pins COM1 I/O ports P17 to P10 Port 1: 8-bit I/O pins.
Type Symbol Name and Function I/O ports PF7 to PF2, Port F: 7-bit I/O pins. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). PH7 to PH0 Port H: 8-bit I/O pins. Input or output can be designated for each bit by means of the port H data direction register (PHDDR).
Section 2 CPU Overview The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control.
32 ÷ 16-bit register-register divide : 1000 ns • Two CPU operating modes Normal mode* Advanced mode Note: * Not available in the H8S/2646 Series. • Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
Normal mode* supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. Note: * Not available in the H8S/2646 Series. • Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
Note: * Not available in the H8S/2646 Series. Figure 2-1 CPU Operating Modes (1) Normal Mode (Not Available in the H8S/2646 Series) The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed.
Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits (figure 2-2).
Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is not pushed onto the stack.
Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). For details of the exception vector table, see section 4, Exception Handling.
Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When EXR is invalid, it is not pushed onto the stack.
(architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2646 Series H'FFFFFFFF (a) Normal Mode* (b) Advanced Mode Note: * Not available in the H8S/2646 Series. Figure 2-6 Memory Map...
Interrupt mask bits Overflow flag CCR: Condition-code register Carry flag Interrupt mask bit MAC: Multiply-accumulate register User bit or interrupt mask bit* Note: * Cannot be used as an interrupt mask bit in the H8S/2646 Series. Figure 2-7 CPU Registers...
2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. Free area SP (ER7) Stack area Figure 2-9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR),...
Bits 2 to 0—Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, Instruction List. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions.
Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data.
Data Type Register Number Data Format Word data Word data Longword data Legend ERn: General register ER General register E General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-10 General Register Data Formats (cont)
2.5.2 Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address.
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. *2 Bcc is the general name for conditional branch instructions. *3 Not available in the H8S/2646 Series. *4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
2.6.2 Instructions and Addressing Modes Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2-2 Combinations of Instructions and Addressing Modes...
2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation General register (destination)* General register (source)* General register* General register (32-bit register) Multiply-accumulate register (32-bit register) (EAd) Destination operand (EAs)
Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE Cannot be used in the H8S/2646 Series. MOVTPE Cannot be used in the H8S/2646 Series. @SP+ → Rn Pops a register from the stack.
Type Instruction Size Function Rd ± Rs → Rd, Rd ± #IMM → Rd Arithmetic B/W/L operations Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register.
Type Instruction Size Function Rd ÷ Rs → Rd Arithmetic DIVXS operations Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16- bit remainder.
Type Instruction Size Function Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Logic B/W/L operations Performs a logical AND operation on a general register and another general register or immediate data. Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd B/W/L Performs a logical OR operation on a general register and another general register or immediate data.
Type Instruction Size Function 1 → (<bit-No.> of <EAd>) Bit- BSET manipulation Sets a specified bit in a general register or memory instructions operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Type Instruction Size Function C ⊕ (<bit-No.> of <EAd>) → C Bit- BXOR manipulation Exclusive-ORs the carry flag with a specified bit in a instructions general register or memory operand and stores the result in the carry flag. C ⊕ [¬ (<bit-No.> of <EAd>) ] → C BIXOR Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand...
Type Instruction Size Function Branch — Branches to a specified address if a specified condition instructions is true. The branching conditions are listed below. Mnemonic Description Condition BRA(BT) Always (true) Always BRN(BF) Never (false) Never C ∨ Z = 0 High C ∨...
Type Instruction Size Function System control TRAPA — Starts trap-instruction exception handling. instructions — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR.
Type Instruction Size Function if R4L ≠ 0 then Block data EEPMOV.B — Repeat @ER5+ → @ER6+ transfer R4L–1 → R4L instruction Until R4L = 0 else next; if R4 ≠ 0 then EEPMOV.W — Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next;...
Figure 2-12 shows examples of instruction formats. (1) Operation field only NOP, RTS, etc. (2) Operation field and register fields ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension MOV.B @(d:16, Rn), Rm, etc. EA (disp) (4) Operation field, effective address extension, and condition field EA (disp) BRA d:16, etc...
Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF 16 bits (@aa:16) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF 32 bits (@aa:32) H'000000 to H'FFFFFF Program instruction 24 bits (@aa:24) address Note: * Not available in the H8S/2646 Series.
0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Note: * Not available in the H8S/2646 Series.
(a) Normal Mode * (b) Advanced Mode Note: * Not available in the H8S/2646 Series. Figure 2-13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address.
Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
End of bus request Bus request Program execution state Bus-released state Sleep mode External interrupt request Software standby mode Exception handling state RES= High STBY= High, RES= Low Reset state Hardware standby mode Power-down state From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: *1 goes low.
2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions.
(2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the reset state when the RES is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address.
(b) Interrupt control mode 2 Advanced mode Reserved (24 bits) (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Notes: *1 Ignored when returning. *2 Not available in the H8S/2646 Series. Figure 2-16 Stack Structure after Exception Handling (Examples)
2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. Bus masters other than the CPU is data transfer controller (DTC).
Basic Timing 2.9.1 Overview The H8S/2600 CPU is driven by a system clock, denoted by the symbol ø. The period from one rising edge of ø to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states.
Bus cycle ø Address bus Held High High HWR, LWR High Data bus High-impedance state Figure 2-18 Pin States during On-Chip Memory Access...
2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access cycle for the on-chip supporting modules. Figure 2-20 shows the pin states. Bus cycle ø...
Bus cycle ø Held Address bus High High HWR, LWR High Data bus High-impedance state Figure 2-20 Pin States during On-Chip Supporting Module Access...
2.9.4 On-Chip HCAN Module Access Timing On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access cycle is shown in figures 2-21 and 2-22, and the pin states in figure 2-23.
Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction. The TAS instruction is not generated by the Hitachi H8S and H8/300 series C/C++ compilers. If the TAS instruction is used as a user-defined intrinsic function, ensure that only register ER0, ER1, ER4, or ER5 is used.
The BCLR instruction can be used to clear the flag of an internal I/O register to 0. In that case, if it is clearly known that the pertinent flag is set to 1 in an interrupt processing routine or other processing, there is no need to read the flag in advance.
3.1.1 Operating Mode Selection The H8S/2646 Series has four operating modes (modes 4 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0).
The H8S/2646 Series can be used only in modes 4 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 Register Configuration...
3.2.2 System Control Register (SYSCR) MACS — INTM1 INTM0 NMIEG — — RAME Initial value — — SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI, and enables or disenables on-chip RAM.
Bit 3—NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG Description An interrupt is requested at the falling edge of NMI input (Initial value) An interrupt is requested at the rising edge of NMI input Bit 2—...
Operating Mode Descriptions 3.3.1 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C, function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals.
*: After reset Address Map in Each Operating Mode A address maps of the H8S/2646 Series are shown in figures 3-1 (1) and 3-1 (2). The address space is 16 Mbytes in modes 4 to 7 (advanced modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 7, Bus...
On-chip RAM* On-chip RAM* On-chip RAM H'FFFFFF H'FFFFFF H'FFFFFF Note: * External addresses can be accessed by clearing th RAME bit in SYSCR to 0. Figure 3-1 (1) Address Map in Each Operating Mode in the H8S/2646, H8S/2646R, H8S/2648, and H8S/2648R...
Modes 4 and 5 Mode 6 Mode 7 (advanced expanded modes (advanced expanded mode (advanced single-chip mode) with on-chip ROM disabled) with on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM H'00FFFF H'00FFFF H'010000 H'010000 External address space Reserved area Reserved area H'01FFFF H'01FFFF...
Section 4 Exception Handling Overview 4.1.1 Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, direct transition, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority.
Reset Trace Exception External interrupts: NMI, IRQ5 to IRQ0 sources Internal interrupts: Interrupts from on-chip supporting modules Interrupts 43 sources in the H8S/2646, H8S/2646R, and H8S/2645 47 sources in the H8S/2648, H8S/2648R, and H8S/2647 Trap instruction Figure 4-1 Exception Sources...
Table 4-2 Exception Vector Table Vector Address Exception Source Vector Number Advanced Mode Reset H'0000 to H'0003 Reserved for system use H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 Trace H'0014 to H'0017 Direct Transition H'0018 to H'001B External interrupt H'001C to H'001F Trap instruction (4 sources)
Immediately after a reset, interrupt control mode 0 is set. When the RES pin goes from low to high, reset exception handling starts. The H8S/2646 Series can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer.
Vector Internal Prefetch of first program fetch processing instruction ø Internal address bus Internal read signal Internal write High signal Internal data (1) (3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) Start address ((5) = (2) (4)) First program instruction Figure 4-2 Reset Sequence (Modes 6 and 7)
4.2.4 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCRA to MSTPCRD are initialized to H'3F, H'FF, H'FF, and B'11****** , respectively, and all modules except the DTC, enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited.
Interrupt exception handling can be requested by seven external sources (NMI, IRQ5 to IRQ0) and internal sources (43 sources in the H8S/2646, H8S/2646R, and H8S/2645, and 47 sources in the H8S/2648, H8S/2648R, and H8S/2647) in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type.
Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code.
(a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return. Figure 4-5 (1) Stack Status after Exception Handling (Normal Modes: Not Available in the H8S/2646 Series) Reserved* (24 bits) (24 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Note: * Ignored on return.
Notes on Use of the Stack When accessing word data or longword data, the H8S/2646 Series assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W...
Overview 5.1.1 Features The H8S/2646 Series controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR).
5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority ISCR determination Internal interrupt request I2 to I0 SWDTEND to Interrupt controller Legend...
5.1.3 Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Interrupt Controller Pins Name Symbol Function Nonmaskable interrupt Input Nonmaskable external interrupt; rising or falling edge can be selected IRQ5 to IRQ0 Input External interrupt Maskable external interrupts; rising, falling, or requests 5 to 0 both edges, or level sensing, can be selected 5.1.4...
Register Descriptions 5.2.1 System Control Register (SYSCR) MACS — INTM1 INTM0 NMIEG — — RAME Initial value — — SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR).
Notes: *1 Reserved. These bits are always read as 1 and cannot be modified. *2 In the H8S/2646, H8S/2646R, and H8S/2645 these are reserved bits that are always read as 1 and should only be written with H'7. In the H8S/2648, H8S/2648R, and...
As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt.
5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH — — — — IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value The ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ5 to IRQ0.
5.2.5 IRQ Status Register (ISR) — — IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt requests.
There are seven external interrupts: NMI and IRQ5 to IRQ0. Of these, NMI and IRQ5 to IRQ0 can be used to restore the H8S/2646 Series from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the status of the CPU interrupt mask bits.
There are 47 sources in the H8S/2648, H8S/2648R, and H8S/2647 and 43 sources in the H8S/2646, H8S/2646R, and H8S/2645 for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts.
Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Vector Address Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority External H'001C High IRQ0 H'0040 IPRA6 to 4 IRQ1 H'0044 IPRA2 to 0 IRQ2 H'0048 IPRB6 to 4 IRQ3 H'004C IRQ4...
Vector Address Origin of Interrupt Vector Advanced Interrupt Source Source Number Mode Priority TGI1A (TGR1A input H'00A0 IPRF2 to 0 High capture/compare match) channel 1 TGI1B (TGR1B input H'00A4 capture/compare match) TCI1V (overflow 1) H'00A8 TCI1U (underflow 1) H'00AC TGI2A (TGR2A input H'00B0 IPRG6 to 4 capture/compare match)
— H'01B8 H'01BC Reserved for system use — H'01C0 — H'01FC Notes: *1 Lower 16 bits of the start address. *2 These vectors are used in the H8S/2648, H8S/2648R, and H8S/2647. They are reserved in the H8S/2646, H8S/2646R, and H8S/2645.
5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2646 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 Interrupt acceptance control Default priority Interrupt source Vector number determination 8-level mask control I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR.
8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level.
5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1.
Program execution status Interrupt generated? Hold pending IRQ0 IRQ1 HCAN Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0...
5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case.  If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
Program execution status Interrupt generated? Level 7 interrupt? Level 6 interrupt? Mask level 6 Level 1 interrupt? or below? Mask level 5 or below? Mask level 0? Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in...
5.4.4 Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Figure 5-7 Interrupt Exception Handling...
5.4.5 Interrupt Response Times The H8S/2646 Series is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high- speed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine.
Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus 16 Bit Bus Internal 2-State 3-State 2-State 3-State Symbol Memory Access Access Access Access Instruction fetch 6+2m Branch address read Stack manipulation Legend m: Number of wait states in an external device access.
TIER0 write cycle by CPU TCIV exception handling ø Internal TIER0 address address bus Internal write signal TCIEV TCFV TCIV interrupt signal Figure 5-8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle.
Interrupt DTC activation request request vector Selection number circuit Select interrupt signal Control logic Clear signal DTCER Interrupt source On-chip Clear signal clear signal supporting module DTVECR SWDTE CPU interrupt clear signal request vector number Determination of priority I, I2 to I0 Interrupt controller Figure 5-9 Interrupt Control for DTC 5.6.3...
Table 5-11 Interrupt Source Selection and Clearing Control Settings Interrupt Source Selection/Clearing Control DTCE DISEL ∆ ∆ ∆ Legend ∆ : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used.
Section 6 PC Break Controller (PBC) Overview The PC break controller (PBC) provides functions that simplify program debugging. Using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. Four break conditions can be set in the PBC: instruction fetch, data read, data write, and data read/write.
6.1.2 Block Diagram Figure 6-1 shows a block diagram of the PC break controller. BARA BCRA Mask control Control Comparator logic Match signal Internal address PC break interrupt Access status Control Comparator logic Match signal Mask control BARB BCRB Figure 6-1 Block Diagram of PC Break Controller...
6.1.3 Register Configuration Table 6-1 shows the PC break controller registers. Table 6-1 PC Break Controller Registers Initial Value Name Abbreviation Reset Address Break address register A BARA H'XX000000 H'FE00 Break address register B BARB H'XX000000 H'FE04 Break control register A BCRA R/(W) H'00...
6.2.2 Break Address Register B (BARB) BARB is the channel B break address register. The bit configuration is the same as for BARA. 6.2.3 Break Control Register A (BCRA) CMFA BAMRA2 BAMRA1 BAMRA0 CSELA1 CSELA0 BIEA Initial value Read/Write R/(W)* Note:* Only a 0 may be written to this bit to clear the flag.
Bits 5 to 3—Break Address Mask Register A2 to A0 (BAMRA2–BAMRA0): These bits specify which bits of the break address (BAA23–BAA0) set in BARA are to be masked. Bit 5 Bit 4 Bit 3 BAMRA2 BAMRA1 BAMRA0 Description All BARA bits are unmasked and included in break conditions (Initial value) BAA0 (lowest bit) is masked, and not included in break conditions...
6.2.4 Break Control Register B (BCRB) BCRB is the channel B break control register. The bit configuration is the same as for BCRA. 6.2.5 Module Stop Control Register C (MSTPCRC) MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value Read/Write MSTPCRC is an 8-bit readable/writable register that performs module stop mode control.
Operation The operation flow from break condition setting to PC break interrupt exception handling is shown in sections 6.3.1, PC Break Interrupt Due to Instrunction Fetch, and 6.3.2, PC Break Interrupt Due to Data Access, taking the example of channel A. 6.3.1 PC Break Interrupt Due to Instruction Fetch 1.
2. Satisfaction of break condition After execution of the instruction that performs a data access on the set address, a PC break request is generated and the condition match flag (CMFA) is set. 3. Interrupt handling After priority determination by the interrupt controller, PC break interrupt exception handling is started.
After execution of the SLEEP instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. After the transition, PC break interrupt handling is executed, then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (C)). 4.
6.3.6 When Instruction Execution is Delayed by One State Caution is required in the following cases, as instruction execution is one state later than usual. 1. When the PBC is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (Bcc d:8, BSR, JSR, JMP, TRAPA, RTE, or RTS) located in on- chip ROM or RAM is always delayed by one state.
6.3.7 Additional Notes 1. When a PC break is set for an instruction fetch at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction: Even if the instruction at the address following a BSR, JSR, JMP, TRAPA, RTE, or RTS instruction is fetched, it is not executed, and so a PC break interrupt is not generated by the instruction fetch at the next address.
Section 7 Bus Controller Overview The H8S/2646 Series has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
7.1.2 Block Diagram Figure 7-1 shows a block diagram of the bus controller. Internal Area decoder address bus ABWCR External bus control signals ASTCR BCRH BCRL Internal control controller signals Bus mode signal Wait WAIT controller WCRH WCRL CPU bus request signal DTC bus request signal Bus arbiter CPU bus acknowledge signal...
7.1.3 Pin Configuration Table 7-1 summarizes the pins of the bus controller. Table 7-1 Bus Controller Pins Name Symbol Function Address strobe Output Strobe signal indicating that address output on address bus is enabled. Read Output Strobe signal indicating that external space is being read.
Register Descriptions 7.2.1 Bus Width Control Register (ABWCR) ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value : Mode 4 Initial value : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access.
ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode.
7.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode.
Bits 3 and 2—Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 5 is accessed...
WCRL Initial value Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 Bit 2 Description Program wait not inserted when external space area 1 is accessed...
7.2.4 Bus Control Register H (BCRH) ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 — — — Initial value BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. BCRH is initialized to H'D0 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access.
Bit 1—Write Data Buffer Enable (WDBE): This bit selects whether or not to use the write buffer function in the external write cycle. Bit 1 WDBE Description Write data buffer function not used (Initial value) Write data buffer function used Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by means of the WAIT pin.
Bits 3 to 0—Address Output Enable 3 to 0 (AE3–AE0): These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM. When a pin is enabled for address output, the address is output regardless of the corresponding DDR setting. When a pin is disabled for address output, it becomes an output port when the corresponding DDR bit is set to 1.
7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode*, it controls a 64-kbyte address space comprising part of area 0. Figure 7-2 shows an outline of the memory map. Note: * Not available in the H8S/2646 Series. H'000000 H'0000...
7.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
7.3.3 Memory Interfaces The H8S/2646 Series memory interfaces comprise a basic bus interface that allows direct connection or ROM, SRAM, and so on, and a burst ROM interface that allows direct connection of burst ROM. The memory interface can be selected independently for each area.
7.3.4 Interface Specifications for Each Area The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (sections 7.4, Basic Bus Interface and 7.5, Burst ROM Interface) should be referred to for further details.
Basic Bus Interface 7.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 7-3). 7.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data...
16-Bit Access Space: Figure 7-4 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions.
7.4.3 Valid Strobes Table 7-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
7.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 7-5 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle ø...
8-Bit 3-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle ø...
16-Bit 2-State Access Space: Figures 7-7 to 7-9 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted.
Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Figure 7-8 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access)
Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Figure 7-9 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access)
16-Bit 3-State Access Space: Figures 7-10 to 7-12 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted.
Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Figure 7-11 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access)
Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Figure 7-12 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access)
7.4.5 Wait Control When accessing external space, the H8S/2646 Series can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T...
Figure 7-13 shows an example of wait state insertion timing. By WAIT pin By program wait ø WAIT Address bus Read Data bus Read data HWR, LWR Write Data bus Write data Note: Downward arrows show the timing of WAIT pin sampling. Figure 7-13 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, 3 program wait state insertion.
Burst ROM Interface 7.5.1 Overview In this LSI, the area 0 external space can be set as burst ROM space and burst ROM interfacing performed. Burst ROM space interfacing allows 16-bit ROM capable of burst access to be accessed at high-speed. The BRSTRM bit of BCRH sets area 0 as burst ROM space.
Full access Burst access ø Low address only changes Address bus Data bus Read data Read data Read data Figure 7.14 (a) Example Burst ROM Access Timing (AST0=BRSTS1=1) Full access Burst access ø Low address only changes Address bus Data bus Read data Read data Read data Figure 7.14 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0)
7.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the burst ROM interface initial cycle (full access). See section 7.4.5, Wait Control. Wait states cannot be inserted in the burst cycle.
Idle Cycle 7.6.1 Operation When the H8S/2646 Series accesses external space , it can insert a 1-state idle cycle (T ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on.
(2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 7-16 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
(3) Relationship between Chip Select (CS*) Signal and Read (RD) Signal Depending on the system’s load conditions, the RD signal may lag behind the CS signal*. An example is shown in figure 7-17. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal.
7.6.2 Pin States During Idle Cycles Table 7-5 shows the pin states during idle cycles. Table 7-5 Pin States During Idle Cycles Pins Pin State A23 to A0 Content identical to immediately following bus cycle D15 to D0 High impedance High level High level High level...
Write Data Buffer Function The H8S/2646 Series has a write data buffer function in the external data bus. Using this function enables external writes to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1.
7.8.1 Overview The H8S/2646 Series has a bus arbiter that arbitrates bus master operations. There are two bus masters, the CPU and DTC which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal.
(3 states), a single data transfer, or a register information write (3 states). Resets and the Bus Controller In a reset, the H8S/2646 Series, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued.
Section 8 Data Transfer Controller (DTC) Overview The H8S/2646 Series includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features • Transfer possible over any number of channels Transfer information is stored in memory ...
8.1.2 Block Diagram Figure 8-1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information.
Register Descriptions 8.2.1 DTC Mode Register A (MRA) Initial value — — — — — — — — *: Undefined MRA is an 8-bit register that controls the DTC operating mode. Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer.
Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 Bit 2 Description Normal mode Repeat mode Block transfer mode — Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0—Reserved: These bits have no effect on DTC operation in the H8S/2646 Series, and should always be written with 0.
8.2.3 DTC Source Address Register (SAR) Initial value — — — — — — — — — — *: Undefined SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 DTC Destination Address Register (DAR) Initial value...
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00.
Bit n—DTC Activation Enable (DTCEn) Bit n DTCEn Description DTC activation by this interrupt is disabled (Initial value) [Clearing conditions] • When the DISEL bit is 1 and the data transfer has ended • When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended...
Bit 7—DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. Bit 7 SWDTE Description DTC software activation is disabled (Initial value) [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not ended •...
Bit 6—Module Stop (MSTPA6): Specifies the DTC module stop mode. Bit 6 MSTPA6 Description DTC module stop mode cleared (Initial value) DTC module stop mode set...
Operation 8.3.1 Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels.
The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed.
8.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. Note: * Not available in the H8S/2646 Series. DTC vector Register information...
Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Vector Vector Interrupt Source Source Number Address DTCE Priority Write to DTVECR Software DTVECR H'0400+ — High (DTVECR [6:0] <<1) IRQ0 External pin H'0420 DTCEA7 IRQ1 H'0422 DTCEA6 IRQ2 H'0424...
110 to 124 H'04DC — H'04FC Notes: *1 DTCE bits with no corresponding interrupt are reserved, and should be written with 0. *2 These vectors are used in the H8S/2648, H8S/2648R, and H8S/2647. They are reserved in the H8S/2646, H8S/2646R, and H8S/2645.
8.3.4 Location of Register Information in Address Space Figure 8-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas.
8.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode.
8.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated.
8.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored.
First block · SAR or DAR or · Block area · Transfer Nth block Figure 8-8 Memory Mapping in Block Transfer Mode...
8.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8-9 shows the memory map for chain transfer.
8.3.9 Operation Timing Figures 8-10 to 8-12 show an example of DTC operation timing. ø DTC activation request request Data transfer Vector read Address Read Write Transfer Transfer information read information write Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) ø...
ø DTC activation request request Data transfer Data transfer Vector read Address Read Write Read Write Transfer Transfer Transfer Transfer information information information information read write read write Figure 8-12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for each execution status.
Table 8-9 Number of States Required for Each Execution Status Chip Chip On-Chip I/O Object to be Accessed Registers External Devices Bus width Access states Execution Vector read — — — 6+2m 2 status Register — — — — — —...
8.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows:  Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.  Set the start address of the register information in the DTC vector address.  Set the corresponding bit in DTCER to 1.
8.3.12 Examples of Use of the DTC Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.  Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0).
Chain Transfer: An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half.
Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0.  Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0).
Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control.
Section 9 I/O Ports Overview The H8S/2646 Series has 13 I/O ports (ports 1 to 3, 5 and A to F, H, J, K), and two input-only port (ports 4 and 9). Table 9-1 summarizes the port functions. The pins of each port also have other functions.
Table 9-1 (1) Port Functions (H8S/2646, H8S/2646R, H8S/2645) Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port 1 • 8-bit I/O P17/PO15/TIOCB2 TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, port /TCLKD TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2), PPG output pins (PO15 to PO8), and interrupt input •...
Port Description Pins Mode 4 Mode 5 Mode 6 Mode 7 Port 5 • 3-bit I/O 3-bit I/O port port Port 9 • 8-bit input A/D converter analog input (AN11 to AN8) and 8-bit input port port P93/AN11 P92/AN10 P91/AN9 P90/AN8 Port A •...