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5.4.5
Interrupt Response Times
The H8S/2646 Series is capable of fast word transfer instruction to on-chip memory, and the
program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-
speed processing.
Table 5-9 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5-9 are explained in table 5-10.
Table 5-9
Interrupt Response Times
No.
Execution Status
1
Interrupt priority determination
2
Number of wait states until executing
instruction ends
3
PC, CCR, EXR stack save
4
Vector fetch
5
Instruction fetch
6
Internal processing
Total (using on-chip memory)
Notes: *1 Two states in case of internal interrupt.
*2 Refers to MULXS and DIVXS instructions.
*3 Prefetch after interrupt acceptance and interrupt handling routine prefetch.
*4 Internal processing after interrupt acceptance and internal processing after vector fetch.
*5 Not available in the H8S/2646 Series.
122
*1
*2
* 3
*4
*5
Normal Mode
INTM1 = 0
INTM1 = 1
3
3
1 to
1 to
(19+2·S
)
(19+2·S
I
2·S
3·S
K
K
S
S
I
I
2·S
2·S
I
I
2
2
11 to 31
12 to 32
Advanced Mode
INTM1 = 0
INTM1 = 1
3
3
1 to
1 to
)
(19+2·S
)
(19+2·S
I
I
2·S
3·S
K
2·S
2·S
I
2·S
2·S
I
2
2
12 to 32
13 to 33
)
I
K
I
I
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