Table of Contents
Advertisement
Section
Page
9.13.2 Register
283
Configuration
15.2.3 Bit
539
Configuration
Register (BCR)
15.2.11 Interrupt
547
Register (IRR)
15.2.16 Unread
555
Message Status
Register (UMSR)
Description
Part F Data Register (PFDR)
Bit
:
7
6
—
PF6DR
Initial value :
0
0
R/W
:
R/W
R/W
2nd line changed as follows
PFDR is an 8-bit readable/writable register that stores output data for the port F
pins (PF6 to PF2, PF0).
6th line changed as follows
Bits 7 and 1 in PFDR are reserved, and only 0 may be written to it.
Figure of Detailed Description of Timing within 1 Bit, HCAN bit rate calculation,
BCR Setting Constraints, Table of Setting Range for TSEG1 and TSEG2 in
BCR
Moved to Bit Rate and Bit Timing Settings in section 15.3.2, Initialization after
Hardware Reset.
Bit 15—Overload Frame Interrupt Flag: Status flag indicating that the HCAN
has transmitted an overload frame.
Bit 15: IRR7
Description
0
[Clearing condition]
Writing 1
1
Overload frame transmission
[Setting conditions]
When overload frame is transmitted
Bit table amended and Note added
UMSR
Bit:
15
14
UMSR7
UMSR6
Initial value:
0
R/W:
R/(W)*
R/(W)*
Bit:
7
UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10
Initial value:
0
R/W:
R/(W)*
R/(W)*
Note: *
Only 1 can be written, to clear the flag.
5
4
PF5DR
PF4DR
PF3DR
0
0
R/W
R/W
R/W
13
12
UMSR5
UMSR4
UMSR3
0
0
0
R/(W)*
R/(W)*
R/(W)*
6
5
4
0
0
0
R/(W)*
R/(W)*
R/(W)*
3
2
1
PF2DR
—
PF0DR
0
0
undefined
R/W
—
R/W
(Initial value)
11
10
9
UMSR2
UMSR1
0
0
0
R/(W)*
R/(W)*
3
2
1
UMSR9
0
0
0
R/(W)*
R/(W)*
0
0
8
UMSR0
0
R/(W)*
0
UMSR8
0
R/(W)*
Advertisement
Table of Contents
