Table of Contents
Advertisement
Type
Symbol
HWR
Bus control
LWR
WAIT
16-bit timer
TCLKD to
pulse unit (TPU)
TCLKA
TIOCA0,
TIOCB0,
TIOCC0,
TIOCD0
TIOCA1,
TIOCB1
TIOCA2,
TIOCB2
TIOCA3,
TIOCB3,
TIOCC3,
TIOCD3
TIOCA4,
TIOCB4
TIOCA5,
TIOCB5
Programmable
PO15 to PO8 Output
pulse generator
(PPG)
22
I/O
Name and Function
Output
High write: A strobe signal that writes to external space
and indicates that the upper half (D15 to D8) of the
data bus is enabled.
Output
Low write: A strobe signal that writes to external space
and indicates that the lower half (D7 to D0) of the data
bus is enabled.
Input
Wait: It is necessary to insert a wait state into the bus
cycle when accessing the external three-state address
space.
Input
Clock input D to A: These pins input an external clock.
I/O
Input capture/ output compare match A0 to D0:
The TGR0A to TGR0D input capture input or output
compare output, or PWM output pins.
I/O
Input capture/ output compare match A1 and B1:
The TGR1A and TGR1B input capture input or output
compare output, or PWM output pins.
I/O
Input capture/ output compare match A2 and B2:
The TGR2A and TGR2B input capture input or output
compare output, or PWM output pins.
I/O
Input capture/ output compare match A3 to D3:
The TGR3A to TGR3D input capture input or output
compare output, or PWM output pins.
I/O
Input capture/output compare match A4 and B4:
The TGR4A and TGR4B input capture input or output
compare output, or PWM output pins.
I/O
Input capture/output compare match A5 and B5:
The TGR5A and TGR5B input capture input or output
compare output, or PWM output pins.
Pulse output 15 to 8: Pulse output pins.
Advertisement
Table of Contents
