Interrupts During Execution Of Eepmov Instruction; Irq Interrupts; Dtc Activation By Interrupt; Overview - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

Interrupts during Execution of EEPMOV Instruction

Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.

With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer

is not accepted until the move is completed.

With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt

exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this

case is the address of the next instruction.

Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the

following coding should be used.

When operating by clock input, acceptance of input to an IRQ pin is synchronized with the clock.

In software standby mode, the input is accepted asynchronously. For details on the input

conditions, see section 23.4.2, Control Signal Timing.

The DTC can be activated by an interrupt. In this case, the following options are available:

• Interrupt request to CPU

• Activation request to DTC

• Selection of a number of the above

For details of interrupt requests that can be used with to activate the DTC, see section 8, Data

Transfer Controller (DTC).

Figure 5-9 shows a block diagram of the DTC interrupt controller.