Hitachi H8S/2646 Hardware Manual page 194

8-Bit 3-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The LWR pin is fixed high. Wait states can be inserted.
ø
Address bus
D15 to D8
Read
D7 to D0
Write
D15 to D8
D7 to D0
Figure 7-6 Bus Timing for 8-Bit 3-State Access Space
162
T
1
AS
RD
HWR
LWR
Bus cycle
T
2
High
Valid
High impedance
T
3
Valid
Invalid