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MSTPCRC—Module Stop Control Register C
Bit
7
MSTPC7
Initial value
1
R/W
Read/Write
PFCR—Pin Function Control Register
Bit
7
—
Initial value
0
Read/Write
R/W
Address Output Enable 3 to 0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note: * In expanded mode of on-chip ROM validity, bits AE3 to AE0 are initialized to B'0000.
In expanded mode of on-chip ROM invalidity, bits AE3 to AE0 are initialized to B'1101.
Address pins A0 to A7 are made address outputs by setting the corresponding DDR bits to 1.
6
5
—
MSTPC5
1
1
—
R/W
6
5
—
—
0
0
R/W
R/W
A8–A23 address output disabled (Initial value*)
A8 address output enabled; A9–A23 address output disabled
A8, A9 address output enabled; A10–A23 address output disabled
A8–A10 address output enabled; A11–A23 address output disabled
A8–A11 address output enabled; A12–A23 address output disabled
A8–A12 address output enabled; A13–A23 address output disabled
A8–A13 address output enabled; A14–A23 address output disabled
A8–A14 address output enabled; A15–A23 address output disabled
A8–A15 address output enabled; A16–A23 address output disabled
A8–A16 address output enabled; A17–A23 address output disabled
A8–A17 address output enabled; A18–A23 address output disabled
A8–A18 address output enabled; A19–A23 address output disabled
A8–A19 address output enabled; A20–A23 address output disabled
A8–A20 address output enabled; A21–A23 address output disabled (Initial value*)
A8–A21 address output enabled; A22, A23 address output disabled
A8–A23 address output enabled
H'FDEA
4
3
MSTPC4
MSTPC3
MSTPC2
1
1
R/W
R/W
Module Stop
0
Module stop mode is cleared
1
Module stop mode is set
H'FDEB
4
3
—
AE3
0
1/0
R/W
R/W
2
1
MSTPC1
MSTPC0
1
1
R/W
R/W
R/W
2
1
AE2
AE1
AE0
1/0
1
1/0
R/W
R/W
R/W
System
0
1
System
0
963
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