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B.2 Functions
882
883
Description
TXACK—Transmit Acknowledge Register
Bit
15
TXACK7
TXACK6
Initial value
0
Read/Write
R/(W)*
R/(W)*
Bit
7
TXACK15
TXACK14
Initial value
0
R/(W)*
R/(W)*
Read/Write
Note added
Note: * Only 1 can be written, to clear the flag.
ABACK—Abort Acknowledge Register H'F80C
Bit
15
ABACK7
ABACK6
Initial value
0
Read/Write
R/(W)*
R/(W)*
Bit
7
ABACK15
ABACK14
Initial value
0
R/(W)*
R/(W)*
Read/Write
Note added
Note: * Only 1 can be written, to clear the flag.
RXPR—Receive Complete Register
Bit
15
RXPR7
RXPR6
Initial value
0
Read/Write
R/(W)*
R/(W)*
Bit
7
RXPR15
RXPR14
Initial value
0
Read/Write
R/(W)*
R/(W)*
Note added
Note: * Only 1 can be written, to clear the flag.
H'F80A
14
13
12
TXACK5
TXACK4
TXACK3
0
0
0
R/(W)*
R/(W)*
6
5
4
TXACK13
TXACK12
TXACK11
0
0
0
R/(W)*
R/(W)*
R/(W)*
14
13
12
ABACK5
ABACK4
ABACK3
0
0
0
R/(W)*
R/(W)*
6
5
4
ABACK13
ABACK12
ABACK11
0
0
0
R/(W)*
R/(W)*
R/(W)*
H'F80E
14
13
12
RXPR5
RXPR4
RXPR3
0
0
0
R/(W)*
R/(W)*
6
5
4
RXPR13
RXPR12
RXPR11
0
0
0
R/(W)*
R/(W)*
R/(W)*
HCAN
11
10
9
TXACK2
TXACK1
0
0
0
R/(W)*
R/(W)*
R/(W)*
3
2
1
TXACK10
TXACK9
0
0
0
R/(W)*
R/(W)*
HCAN
11
10
9
ABACK2
ABACK1
0
0
0
R/(W)*
R/(W)*
R/(W)*
3
2
1
ABACK10
ABACK9
0
0
0
R/(W)*
R/(W)*
HCAN
11
10
9
RXPR2
RXPR1
0
0
0
R/(W)*
R/(W)*
R/(W)*
3
2
1
RXPR10
RXPR9
0
0
0
R/(W)*
R/(W)*
8
—
0
—
0
TXACK8
0
R/(W)*
8
—
0
—
0
ABACK8
0
R/(W)*
8
RXPR0
0
R/(W)*
0
RXPR8
0
R/(W)*
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