Timing Of Setting Of Watchdog Timer Overflow Flag (Wovf) - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

Overflow signal

(internal signal)

Timing of Setting of Watchdog Timer Overflow Flag (WOVF)

In the WDT0, the WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. If

TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated

for the entire H8S/2646 Series chip. Figure 12-7 shows the timing in this case.

Overflow signal

(internal signal)

Internal reset

Figure 12-6 Timing of Setting of OVF

Figure 12-7 Timing of Setting of WOVF

518 states (WDT0)

515/516 states (WDT1)