Exiting Watch Mode; Notes - Hitachi H8S/2646 Hardware Manual

22.8.2

Exiting Watch Mode

Watch mode is exited by any interrupt (WOVI interrupt, NMI pin, or IRQ0 to IRQ5), or signals at
the RES, or STBY pins.
Exiting Watch Mode by Interrupts: When an interrupt occurs, watch mode is exited and a
transition is made to high-speed mode or medium-speed mode when the LPWRCR LSON bit = 0
or to sub-active mode when the LSON bit = 1. When a transition is made to high-speed mode, a
stable clock is supplied to all LSI circuits and interrupt exception processing starts after the time
set in SBYCR STS2 to STS0 has elapsed. In the case of IRQ0 to IRQ5 interrupts, no transition is
made from watch mode if the corresponding enable bit has been cleared to 0, and, in the case of
interrupts from the internal supporting modules, the interrupt enable register has been set to
disable the reception of that interrupt, or is masked by the CPU.
See section 22.6.3, Setting Oscillation Stabilization Time after Clearing Software Standby Mode,
for how to set the oscillation stabilization time when making a transition from watch mode to
high-speed mode.
Exiting Watch Mode by RES pins: For exiting watch mode by the RES pins, see, Clearing with
the RES pins in section 22.6.2, Clearing Software Standby Mode.
Exiting Watch Mode by STBY pin: When the STBY pin level is driven Low, a transition is
made to hardware standby mode.
22.8.3

Notes

I/O Port Status: The status of the I/O ports is retained in watch mode. Also, when the OPE bit is
set to 1, the address bus and bus control signals continue to be output. Therefore, when a High
level is output, the current consumption is not diminished by the amount of current to support the
High level output.
Current Consumption when Waiting for Oscillation Stabilization: The current consumption
increases during stabilization of oscillation.
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