Table of Contents
Advertisement
9.9.2
Register Configuration
Table 9-16 shows the port B register configuration.
Table 9-16 Port B Registers
Name
Port B data direction register
Port B data register
Port B register
Port B MOS pull-up control register
Port B open-drain control register
Note: * Lower 16 bits of the address.
Port B Data Direction Register (PBDDR)
Bit
:
7
PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
Initial value :
0
R/W
:
W
PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port B. PBDDR cannot be read; if it is, an undefined value will be read.
PBDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
Port B Data Register (PBDR)
Bit
:
7
PB7DR
Initial value :
0
R/W
:
R/W
PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to
PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior
state in software standby mode.
262
Abbreviation
PBDDR
PBDR
PORTB
PBPCR
PBODR
6
5
0
0
W
W
6
5
PB6DR
PB5DR
PB4DR
0
0
R/W
R/W
R/W
Initial Value
W
H'00
R/W
H'00
R
Undefined
R/W
H'00
R/W
H'00
4
3
0
0
W
W
4
3
PB3DR
PB2DR
0
0
R/W
R/W
R/W
Address*
H'FE3A
H'FF0A
H'FFBA
H'FE41
H'FE48
2
1
0
0
W
W
W
2
1
PB1DR
PB0DR
0
0
R/W
R/W
0
0
0
0
Advertisement
Table of Contents
