Operation; Watchdog Timer Operation - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

Operation

To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1. Software

must prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before

overflow occurs. This ensures that TCNT does not overflow while the system is operating

normally. If TCNT overflows without being rewritten because of a system malfunction or other

error, an internal reset is issued, in the case of WDT0, if the RSTE bit in RSTCSR is set to 1.

The internal reset signal is output for 518 states.

If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a

WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0.

In the case of WDT1, the chip is reset, or an NMI interrupt request is generated, for 516 system

clock periods (516ø) (515 or 516 clock periods when the clock source is øSUB (PSS = 1)). This is

illustrated in figure 12-4 (b).

An NMI request from the watchdog timer and an interrupt request from the NMI pin are both

treated as having the same vector. So, avoid handling an NMI request from the watchdog timer

and an interrupt request from the NMI pin at the same time.

Internal reset signal *

: Timer mode select bit

: Timer enable bit

Note: * The internal reset signal is generated only if the RSTE bit is set to 1.

Figure 12-4 (a) WDT0 Watchdog Timer Operation

internal reset is