Table of Contents
Advertisement
TIOR3H—Timer I/O Control Register 3H
Bit
7
IOB3
Initial value
0
Read/Write
R/W
TGR3B I/O Control
0
0
0
0
TGR3B is
output
1
compare
1
0
register
1
1
0
0
1
1
0
1
1
0
0
0
TGR3B is
input
1
capture
1
*
register
1
*
*
Note: *1 When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and ø/1 is used as the
TCNT4 count clock, this setting is invalid and input capture is not generated.
984
6
5
IOB2
IOB1
0
0
R/W
R/W
TGR3A I/O Control
0
0
0
0
TGR3A is
output
1
compare
1
0
register
1
1
0
0
1
1
0
1
1
0
0
0
TGR3A is
input
1
capture
1
*
register
1
*
*
Output disabled
Initial output is 0
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Output disabled
Initial output is 1
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Capture input
Input capture at rising edge
source is
Input capture at falling edge
TIOCB3 pin
Input capture at both edges
Capture input
Input capture at TCNT4 count-up/
source is channel
count-down
4/count clock
H'FE82
4
3
IOB0
IOA3
IOA2
0
0
R/W
R/W
R/W
Output disabled
Initial output is 0
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Output disabled
Initial output is 1
0 output at compare match
output
1 output at compare match
Toggle output at compare match
Capture input
Input capture at rising edge
source is
Input capture at falling edge
TIOCA3 pin
Input capture at both edges
Capture input
Input capture at TCNT4 count-up/
source is channel
count-down
4/count clock
*1
*: Don't care
2
1
0
IOA1
IOA0
0
0
0
R/W
R/W
*: Don't care
TPU3
Advertisement
Table of Contents
