Hitachi H8S/2646 Hardware Manual page 1021

TCR4—Timer Control Register 4
Bit 7
—
Initial value 0
Read/Write —
Counter Clear
0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input capture
1 0 TCNT cleared by TGRB compare match/input capture
1 TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation*
Note: * Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
Note: Bit 7 is reserved in channel 4.
It is always read as 0 and cannot be modified.
6 5
CCLR1 CCLR0 CKEG1
0 0
R/W R/W
Time Prescaler
0 0
1
1 0
1
Note: This setting is ignored when channel 4 is in phase
Clock Edge
0 0 Count at rising edge
1 Count at falling edge
1 — Count at both edges
Note: Internal clock edge selection is valid when the input
clock is ø/4 or slower. This setting is ignored if the
input clock is ø/1, or when overflow/underflow of
another channel is selected.
H'FE90
4 3
CKEG0 TPSC2
0 0
R/W R/W R/W
0 Internal clock: counts on ø/1
1 Internal clock: counts on ø/4
0 Internal clock: counts on ø/16
1 Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
0
External clock: counts on TCLKC pin input
1
Internal clock: counts on ø/1024
0
Counts on TCNT5 overflow/underflow
1
counting mode.
2 1 0
TPSC1 TPSC0
0 0 0
R/W R/W
TPU4
989