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9.10.2
Register Configuration
Table 9-19 shows the port C register configuration.
Table 9-19 Port C Registers
Name
Port C data direction register
Port C data register
Port C register
Port C MOS pull-up control register
Port C open-drain control register
Note: * Lower 16 bits of the address.
Port C Data Direction Register (PCDDR)
Bit
:
7
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Initial value :
0
R/W
:
W
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port C. PCDDR cannot be read; if it is, an undefined value will be read.
PCDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when the mode is changed to software standby
mode.
Port C Data Register (PCDR)
Bit
:
7
PC7DR
Initial value :
0
R/W
:
R/W
PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to
PC0).
PCDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Abbreviation
PCDDR
PCDR
PORTC
PCPCR
PCODR
6
5
0
0
W
W
6
5
PC6DR
PC5DR
PC4DR
0
0
R/W
R/W
R/W
Initial Value
W
H'00
R/W
H'00
R
Undefined
R/W
H'00
R/W
H'00
4
3
0
0
W
W
4
3
PC3DR
PC2DR
0
0
R/W
R/W
R/W
Address*
H'FE3B
H'FF0B
H'FFBB
H'FE42
H'FE49
2
1
0
0
0
0
W
W
W
2
1
0
PC1DR
PC0DR
0
0
0
R/W
R/W
267
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