Hcan Halt Mode - Hitachi H8S/2646 Hardware Manual

HCAN sleep mode is entered by setting the HCAN sleep mode bit (MCR5) to 1 in the master
control register (MCR). If the CAN bus is operating, the transition to HCAN sleep mode is
delayed until the bus becomes idle.
Either of the following methods of clearing HCAN sleep mode can be selected by making a setting
in the MCR7 bit.
1. Clearing by software
2. Clearing by CAN bus operation
Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus
communication is enabled again.
Clearing by software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.
Clearing by CAN bus operation: Clearing by CAN bus operation occurs automatically when the
CAN bus performs an operation and this change is detected. The first message is not received in
the mailbox and normal receiving starts from the next message. When a change is detected on the
CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is set in the interrupt
register (IRR). If the bus interrupt mask (IMR12) in the interrupt mask register (IMR) is set to the
interrupt enable value at this time, an interrupt can be sent to the CPU.
15.3.6

HCAN Halt Mode

The HCAN halt mode is provided to enable mailbox settings to be changed without performing an
HCAN hardware or software reset. Figure 15-12 shows a flowchart of the HCAN halt mode.
MBCR setting
CAN bus communication possible
582
MCR1 = 1
Bus idle?
Yes
MCR1 = 0
Figure 15-12 HCAN Halt Mode Flowchart
No
: Settings by user
: Processing by hardware