Internal Interrupts; Interrupt Exception Handling Vector Table - Hitachi H8S/2646 Hardware Manual

Hitachi 16-bit single-chip microcomputer h8s/2646 series

Table of Contents

Figure 5-3 shows the timing of setting IRQnF.

The vector numbers for IRQ5 to IRQ0 interrupt exception handling are 21 to 16.

Detection of IRQ5 to IRQ0 interrupts does not depend on whether the relevant pin has been set for

input or output. However, when a pin is used as an external interrupt input pin, do not clear the

corresponding DDR to 0 and use the pin as an I/O pin for another function.

Internal Interrupts

There are 47 sources in the H8S/2648, H8S/2648R, and H8S/2647 and 43 sources in the

H8S/2646, H8S/2646R, and H8S/2645 for internal interrupts from on-chip supporting modules.

• For each on-chip supporting module there are flags that indicate the interrupt request status,

and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1

for a particular interrupt source, an interrupt request is issued to the interrupt controller.

• The interrupt priority level can be set by means of IPR.

• The DTC can be activated by a TPU, SCI, or other interrupt request. When the DTC is

activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected.

Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities.

For default priorities, the lower the vector number, the higher the priority.

Priorities among modules can be set by means of the IPR. The situation when two or more

modules are set to the same priority, and priorities within a module, are fixed as shown in

Figure 5-3 Timing of Setting IRQnF