Serial Status Register (Ssr) - Hitachi H8S/2646 Hardware Manual

14.2.2

Serial Status Register (SSR)

Bit : 7
TDRE
Initial value : 1
R/W : R/(W)*
Note: * Only 0 can be written, to clear these flags.
Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting
conditions for bit 2, TEND, are also different.
Bits 7 to 5—Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial
Status Register (SSR).
Bit 4—Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the
error signal sent back from the receiving end in transmission. Framing errors are not detected in
Smart Card interface mode.
Bit 4
ERS Description
0 Normal reception, with no error signal
[Clearing conditions]
•
Upon reset, and in standby mode or module stop mode
•
When 0 is written to ERS after reading ERS = 1
1 Error signal sent from receiver indicating detection of parity error
[Setting condition]
When the low level of the error signal is sampled
Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous
state.
6 5
RDRF ORER
0 0
R/(W)* R/(W)* R/(W)*
4 3
ERS PER TEND
0 0
R/(W)*
2 1 0
MPB MPBT
1 0 0
R R R/W
(Initial value)
505