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BCRA—Break Control Register A
BCRB—Break Control Register B
Bit
7
CMFA
Initial value
0
Read/Write
R/(W)*
Break Address Mask Register
0
0
1
1
0
1
CPU Cycle/DTC Cycle Select A
0 PC break is performed when CPU is bus master
1
PC break is performed when CPU or DTC is bus master
Condition Match Flag A
0 [Clearing condition]
When 0 is written to CMFA after reading CMFA = 1
1
[Setting condition]
When a condition set for channel A is satisfied
Notes:
BCRB is the channel B break control register.
The bit configuration is the same as for BCRA.
* Only a 0 may be written to this bit to clear the flag.
966
6
5
CDA
BAMRA2
0
0
R/W
R/W
Break Condition Select
0
0
Instruction fetch is used as break condition
1
Data read cycle is used as break condition
1
0
Data write cycle is used as break condition
1
Data read/write cycle is used as break condition
0
All BARA bits are unmasked and included in break conditions
1
BAA0 (lowest bit) is masked, and not included in break conditions
0
BAA1–0 (lower 2 bits) are masked, and not included in break conditions
1
BAA2–0 (lower 3 bits) are masked, and not included in break conditions
BAA3–0 (lower 4 bits) are masked, and not included in break conditions
0
BAA7–0 (lower 8 bits) are masked, and not included in break conditions
1
BAA11–0 (lower 12 bits) are masked, and not included in break conditions
0
BAA15–0 (lower 16 bits) are masked, and not included in break conditions
1
H'FE08
H'FE09
4
3
BAMRA1
BAMRA0
CSELA1
0
0
R/W
R/W
Break Interrupt Enable
0 PC break interrupts are disabled
1
PC break interrupts are enabled
2
1
CSELA0
BIEA
0
0
R/W
R/W
R/W
PBC
PBC
0
0
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