Mailbox Interrupt Mask Register (Mbimr) - Hitachi H8S/2646 Hardware Manual

15.2.12 Mailbox Interrupt Mask Register (MBIMR)

The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing
flags that enable or disable individual mailbox (buffer) interrupt requests.
MBIMR
Bit:
Initial value:
R/W:
Bit:
MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8
Initial value:
R/W:
Bits 15 to 0—Mailbox Interrupt Mask (MBIMRx): Flags that enable or disable individual
mailbox interrupt requests.
Bit x: MBIMRx
0
1
15 14
MBIMR7 MBIMR6 MBIMR5
1 1
R/W R/W
7 6
1 1
R/W R/W
Description
[Transmitting]
Interrupt request to CPU due to TXPR clearing
[Receiving]
Interrupt request to CPU due to RXPR setting
Interrupt requests to CPU disabled
13 12 11
MBIMR4 MBIMR3
1 1
R/W R/W R/W
5 4
1 1
R/W R/W R/W
10 9
MBIMR2 MBIMR1 MBIMR0
1 1 1
R/W R/W
3 2 1
1 1 1
R/W R/W
8
1
R/W
0
1
R/W
(Initial value)
(x = 15 to 0)
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