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9.13.2
Register Configuration
Table 9-28 shows the port F register configuration.
Table 9-28 Port F Registers
Name
Port F data direction register
Port F data register
Port F register
Notes: *1 Lower 16 bits of the address.
*2 Initial value depends on the mode.
Port F Data Direction Register (PFDDR)
Bit
:
7
PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR
Modes 4 to 6
Initial value :
1
R/W
:
W
Mode 7
Initial value :
0
R/W
:
W
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a reset, and in hardware standby mode, to H'80 in modes 4 to 6, and to
H'00 in mode 7. It retains its prior state in software standby mode. The OPE bit in SBYCR is used
to select whether the bus control output pins retain their output state or become high-impedance
when a transition is made to software standby mode.
PFDDR bit 1 is reserved.
282
Abbreviation R/W
PFDDR
W
PFDR
R/W
PORTF
R
6
5
0
0
W
W
W
0
0
W
W
W
Initial Value
* 2
H'80/H'00
H'00
Undefined
4
3
2
0
0
0
W
W
0
0
0
W
W
*1
Address
H'FE3E
H'FF0E
H'FFBE
1
0
—
PF0DDR
0
undefined
—
W
0
undefined
—
W
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