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TCSR0—Timer Control/Status Register 0
Bit
7
OVF
Initial value
0
Read/Write
R/(W)*
Timer Mode Select
0
1
Note: * For details see section 12.2.3, Reset Control/Status Register (RSTCSR).
Overflow Flag
0
[Clearing conditions]
• Cleared when 0 is written to the TME bit (Only applies to WDT1)
• Cleared by reading TCSR when OVF = 1, then write 0 in OVF
1
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset)
Note: * Only a 0 may be written to this bit to clear the flag.
TCSR0 register differs from other registers in being more difficult to write to.
For details see section 12.2.4, Notes on Register Access.
6
5
WT/IT
TME
0
0
R/W
R/W
Clock Select 2 to 0
CKS2 CKS1 CKS0
0
1
Note: * An overflow period is the time interval between the
Timer Enable
0
TCNT is initialized to H'00 and halted
1
TCNT counts
Interval timer mode: WDT0 requests an interval timer interrupt (WOVI) from
the CPU when the TCNT overflows
Watchdog timer mode: A reset is issued when the TCNT overflows if the
RSTE bit of RSTCSR is set to 1*
H'FF74(W), H'FF74(R)
4
3
—
—
1
1
—
—
Clock
0
0
ø/2
1
ø/64
1
0
ø/128
1
ø/512
0
0
ø/2048
1
ø/8192
1
0
ø/32768
1
ø/131072
start of counting up from H'00 on the TCNT and the
occurrence of a TCNT overflow.
2
1
CKS2
CKS1
CKS0
0
0
R/W
R/W
R/W
Overflow Period*
(where ø = 20 MHz)
25.6 µs
819.2 µs
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
WDT0
0
0
1029
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