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Example: With a 1 Mb/s baud rate and a 20 MHz input clock:
1 Mb/s =
2 × (0 + 1) × (3 + 4 + 3)
Set Values
f
= 20 MHz
CLK
BRP = 0 (B'000000)
TSEG1 = 4 (B'0100)
TSEG2 = 3 (B'011)
1-bit time
SYNC_SEG
1
Legend
SYNC_SEG: Segment for establishing synchronization of nodes on the CAN bus. (Normal
bit edge transitions occur in this segment.)
PRSEG:
Segment for compensating for physical delay between networks.
PHSEG1:
Buffer segment for correcting phase drift (positive). (This segment is extended
when synchronization (resynchronization) is established.)
PHSEG2:
Buffer segment for correcting phase drift (negative). (This segment is
shortened when synchronization (resynchronization) is established.)
Note: * The time quanta values of TSEG1 and TSEG2 become the value of TSEG + 1.
Figure 15-6 Detailed Description of Timing within 1 Bit
HCAN bit rate calculation:
Bit rate =
2 × (BRP + 1) × (3 + TSEG1 + TSEG2)
Note: f
= ø (system clock)
CLK
The BCR values are used for BRP, TSEG1, and TSEG2.
BCR Setting Constraints
TSEG1 > TSEG2 ≥ SJW
These constraints allow the setting range shown in table 15-4 for TSEG1 and TSEG2 in BCR.
566
20 MHz
Actual Values
—
System clock × 2
5TQ
4TQ
1-bit time (8–25 time quanta)
PRSEG
TSEG1 (time segment 1)*
2–16
f
CLK
(SJW = 0 to 3)
PHSEG1
PHSEG2
TSEG2 (time segment 2)*
Quantum
2–8
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