Hitachi H8S/2646 Hardware Manual page 513

Hitachi 16-bit single-chip microcomputer h8s/2646 series
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Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive operations are performed, however, the
serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to
perform receive operations in units of one character, you should select an external clock as the
clock source.
Data Transfer Operations:
• SCI initialization (clocked synchronous mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0,
then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared
to 0 before making the change using the following procedure. When the TE bit is cleared to 0,
the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not
change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Figure 13-15 shows a sample SCI initialization flowchart.
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
Set data transfer format in
SMR and SCMR
Set value in BRR
1-bit interval elapsed?
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
[1]
[2]
[3]
Wait
No
Yes
[4]
Figure 13-15 Sample SCI Initialization Flowchart
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
481

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