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TCR0—Timer Control Register 0
Bit
7
CCLR2
Initial value
0
Read/Write
R/W
Counter Clear
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Notes: *1
*2
1010
6
5
CCLR1
CCLR0
0
0
R/W
R/W
Time Prescaler
0
1
Clock Edge
0
0
Count at rising edge
1
Count at falling edge
1
—
Count at both edges
Note: Internal clock edge selection is valid when the input clock
is ø/4 or slower. This setting is ignored if the input clock is ø/1,
or when overflow/underflow of another channel is selected.
TCNT clearing disabled
TCNT cleared by TGRA compare match/input capture
TCNT cleared by TGRB compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
TCNT clearing disabled
TCNT cleared by TGRC compare match/input capture
TCNT cleared by TGRD compare match/input capture
TCNT cleared by counter clearing for another channel
performing synchronous clearing/synchronous operation
Synchronous operation setting is performed by setting the
SYNC bit in TSYR to 1.
When TGRC or TGRD is used as a buffer register, TCNT is
not cleared because the buffer register setting has priority,
and compare match/input capture does not occur.
H'FF10
4
3
CKEG1
CKEG0
TPSC2
0
0
R/W
R/W
0
0
Internal clock: counts on ø/1
1
Internal clock: counts on ø/4
1
0
Internal clock: counts on ø/16
1
Internal clock: counts on ø/64
External clock: counts on TCLKA pin input
0
0
External clock: counts on TCLKB pin input
1
External clock: counts on TCLKC pin input
1
0
External clock: counts on TCLKD pin input
1
2
1
TPSC1
TPSC0
0
0
R/W
R/W
R/W
*1
*2
*2
*1
TPU0
0
0
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