Table of Contents
Advertisement
2.9.3
On-Chip Supporting Module Access Timing
The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits
wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the
access cycle for the on-chip supporting modules. Figure 2-20 shows the pin states.
ø
Internal address bus
Internal read signal
Read
access
Internal data bus
Internal write signal
Write
access
Internal data bus
Figure 2-19 On-Chip Supporting Module Access Cycle
Bus cycle
T1
Address
Read data
Write data
T2
73
Advertisement
Table of Contents
