Timer Mode Register (Tmdr) - Hitachi H8S/2646 Hardware Manual

10.2.2

Timer Mode Register (TMDR)

Channel 0: TMDR0
Channel 3: TMDR3
Bit : 7
—
Initial value : 1
R/W : —
Channel 1: TMDR1
Channel 2: TMDR2
Channel 4: TMDR4
Channel 5: TMDR5
Bit : 7
—
Initial value : 1
R/W : —
The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers
are initialized to H'C0 by a reset, and in hardware standby mode.
TMDR register settings should be made only when TCNT operation is stopped.
Bits 7 and 6—Reserved: It is always read as 1 and cannot be modified.
Bit 5—Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and
cannot be modified.
Bit 5
BFB Description
0 TGRB operates normally
1 TGRB and TGRD used together for buffer operation
6 5
— BFB BFA
1 0
— R/W R/W
6 5
— — —
1 0
— — —
4 3 2
MD3 MD2
0 0 0
R/W R/W
4 3 2
MD3 MD2
0 0 0
R/W R/W
1 0
MD1 MD0
0 0
R/W R/W
1 0
MD1 MD0
0 0
R/W R/W
(Initial value)
309