Notes On Pc Break Interrupt Handling; Operation In Transitions To Power-Down Modes - Hitachi H8S/2646 Hardware Manual

2. Satisfaction of break condition
 After execution of the instruction that performs a data access on the set address, a PC break
request is generated and the condition match flag (CMFA) is set.
3. Interrupt handling
 After priority determination by the interrupt controller, PC break interrupt exception
handling is started.
6.3.3

Notes on PC Break Interrupt Handling

1. The PC break interrupt is shared by channels A and B. The channel from which the request
was issued must be determined by the interrupt handler.
2. The CMFA and CMFB flags are not cleared to 0, so 0 must be written to CMFA or CMFB
after first reading the flag while it is set to 1. If the flag is left set to 1, another interrupt will be
requested after interrupt handling ends.
3. A PC break interrupt generated when the DTC is the bus master is accepted after the bus has
been transferred to the CPU by the bus controller.
6.3.4

Operation in Transitions to Power-Down Modes

The operation when a PC break interrupt is set for an instruction fetch at the address after a
SLEEP instruction is shown below.
1. When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
sleep mode, or from subactive mode to subsleep mode:
After execution of the SLEEP instruction, a transition is not made to sleep mode or subsleep
mode, and PC break interrupt handling is executed. After execution of PC break interrupt
handling, the instruction at the address after the SLEEP instruction is executed (figure 6-2
(A)).
2. When the SLEEP instruction causes a transition from high-speed (medium-speed) mode to
subactive mode:
After execution of the SLEEP instruction, a transition is made to subactive mode via direct
transition exception handling. After the transition, PC break interrupt handling is executed,
then the instruction at the address after the SLEEP instruction is executed (figure 6-2 (B)).
3. When the SLEEP instruction causes a transition from subactive mode to high-speed (medium-
speed) mode:
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