Instruction Set; Overview - Hitachi H8S/2646 Hardware Manual

2.6

Instruction Set

2.6.1

Overview

The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2-1.
Table 2-1 Instruction Classification
Function Instructions
Data transfer MOV
POP
LDM, STM
MOVFPE
Arithmetic ADD, SUB, CMP, NEG
operations
ADDX, SUBX, DAA, DAS
INC, DEC
ADDS, SUBS
MULXU, DIVXU, MULXS, DIVXS
EXTU, EXTS
TAS
MAC, LDMAC, STMAC, CLRMAC
Logic operations AND, OR, XOR, NOT
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
Branch Bcc
System control TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
Block data transfer EEPMOV
Notes: B-byte size; W-word size; L-longword size.
*1 POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
*2 Bcc is the general name for conditional branch instructions.
*3 Not available in the H8S/2646 Series.
*4 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
44
*1 *1
, PUSH
*3 *3
, MOVTPE
* 4
*2
, JMP, BSR, JSR, RTS
Size Types
BWL 5
WL
L
B
BWL 23
B
BWL
L
BW
WL
B
—
BWL 4
8
B 14
— 5
9
— 1
Total: 69